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| Title: | SABLE SYSTEM PUBLIC DISCUSSION |
|
| Moderator: | COSMIC::PETERSON |
|
| Created: | Mon Jan 11 1993 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 2614 |
| Total number of notes: | 10244 |
2523.0. "Need help ... Machine check 660" by TKTVFS::IKEDA_J (ZOSO) Tue Feb 18 1997 06:00
I have a system intermitttantly crashes with
Machine Check 660.
Please help on decording this error.
problem system is AS2100-5/250(RM)
- 3 CPUs
- 512 * 3 Memory
- ATI MACH64
- KZPSA * 2,DEFPA on PCI
Jotaro Ikeda/Japan MCS
DECevent V2.2
******************************** ENTRY 2 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 4.
Timestamp of occurrence 18-FEB-1997 15:54:22
Host name stfep2
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000003
CPU logging event (mperr) x00000002
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 302. ASCII Panic Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 1. Panic
ASCII Message mem_msctl = 0000080000000800
******************************** ENTRY 3 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 3.
Timestamp of occurrence 18-FEB-1997 15:54:22
Host name stfep2
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000003
CPU logging event (mperr) x00000001
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000022 Machine Check Frame
CPU Number Logging Event 1.
- ALPHA EV5 COMMON REGS -
Flags: x00000001
Machine Check Error Code x00000202 CPU Detected Unrecoverable Error
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x0000000000000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 xFFFFFFFFAF574000
PALTEMP1 xFFFFFC0015476100
PALTEMP2 xFFFFFC00004E10F0
PALTEMP3 x0000000000004800
PALTEMP4 x0000033F000C0001
PALTEMP5 x00000000000C0000
PALTEMP6 x000000000000000C
PALTEMP7 xFFFFFC00004E0B70
PALTEMP8 x1F1E161514020100
PALTEMP9 xFFFFFC00004E0E60
PALTEMP10 xFFFFFC0000303500
PALTEMP11 xFFFFFC00004E0CC0
PALTEMP12 xFFFFFC00004E1060
PALTEMP13 x0000012000000120
PALTEMP14 x0000000000000001
PALTEMP15 x0000000000000000
PALTEMP16 x0000020306600101
PALTEMP17 x0000000000000000
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFFAF59F978
PALTEMP20 x0000000000940000
PALTEMP21 xFFFFFC00004E1090
PALTEMP22 xFFFFFC00006D72B0
PALTEMP23 x0000000056D85A58
Exception Address Reg xFFFFFC0000303500
Native-mode Instruction
Exception PC x3FFFFF00000C0D40
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode: x0000000000000005
Interrupt Summary Reg x0000000000000000
AST Requests 3-0: x0000000000000000
IBOX Ctrl and Status Reg x0000004160800000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFF804AAC08
Memory Mgmt Flt Sts Reg x00000000000148D0
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field: x0000000000000003
Fault Inst Opcode: x0000000000000029
Scache Address Reg xFFFFFF000001916F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF80130DCFFF
Last Bcache Access Resulted in a Miss.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Clear.
Value of Tag Control Dirty Bit is Set.
Value of Tag Control Shared Bit is Set.
Value of Tag Control Valid Bit is Set.
Value of Parity Bit Covering Tag Store
Address Bits is Clear.
Tag Address<38:20> Is: x0000000000000130
Ext Interface Address Reg xFFFFFFD917FE4D1F
Fill Syndrome Reg x0000000000007BFA
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF000072823F
- SYSTEM SPECIFIC REGS -
Configuration Reg (R0) x380000F238000002
LOW LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 12 Clr: Cmd/Data NOACK are Errors
Bit 24 Clr: IDLEBC Assert in Last Cycle 4
Bit 25 Clr: IDLEBC Assert During Cycle 4
Bit 27 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
HIGH LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 36 Set: Rx IPL31 on CBus CERR Assert
Bit 37 Set: Rx HALT on CBus SYS_EVENT
Bit 38 Set: Rx HALT on IIRR CSR24 HALT Req
Bit 39 Set: Rx INTERPROC INT on Write to
IIRR CSR24 INTERPROC INT Req
Bit 44 Clr: Cmd/Data NOACK are Errors
Bit 56 Clr: IDLEBC Assert in Last Cycle 4
Bit 57 Clr: IDLEBC Assert During Cycle 4
Bit 59 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
Error Summary Reg (R1) x0000000000000000
EVB Control Register (R2) x0000006100000061
LOW LONGWORD Slice Follows
Bit 0 Set: Enable Addr-Cmd Parity Checking
Bit 5 Set: Enable Bcache ECC Corr QW0/QW2
Bit 6 Set: Enable ECC Check - QW0/QW2 Data
HIGH LONGWORD Slice Follows
Bit 32 Set: Enable Addr-Cmd Parity Check
Bit 37 Set: Enable Bcache ECC Corr QW1/QW3
Bit 38 Set: Enable ECC Check-QW1/QW3 Data
Victim Error Addr (R3) x0130000601300006
LOW LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000001300006
HIGH LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000001300006
Correctable Err Reg (R4) x0000000000000000
LOW LONGWORD Slice Follows
QW0 ECC Syndrome: No Syndrome Bits Set
QW2 ECC Syndrome: No Syndrome Bits Set
HIGH LONGWORD Slice Follows
QW1 ECC Syndrome: No Syndrome Bits Set
QW3 ECC Syndrome: No Syndrome Bits Set
Correctable Err Addr (R5) xB810000A00000662
LOW LONGWORD Slice Follows
Bit 32 Clr: EV-Bus Bit 39, IO Bit, Clr
EVB<34:4> Corr Err Adr x0000000000000662
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005810000A
Uncorrectable Error (R6) x8000000080000000
LOW LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW0 Uncorr ECC Syndrome x0000000000000000
QW2 Uncorr ECC Syndrome x0000000000000000
HIGH LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW1 Uncorr ECC Syndrome x0000000000000000
QW3 Uncorr ECC Syndrome x0000000000000000
Uncorrectable Err Adr(R7) xB810000EB810000E
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005810000E
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005810000E
EVB Reserve Register (R8) x0000000000000000
Duplicate Tag Control(R9) x0000011100000111
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Enable
Bit 4 Set: Enable Tag Ctrl Parity Checking
Bit 8 Set: Enable Tag Parity Checking
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Enable
Bit 36 Set: Enable Tag Ctl Parity Checking
Bit 40 Set: Enable Tag Parity Checking
Duplicate Tag Error (R10) x00000000000001A0
LOW LONGWORD Slice Follows
Dup Tag Store Err Adr x000000000000000D
Dup Tag Test Control(R11) x0000000000000000
LOW LONGWORD Slice Follows
Bit 3 Clr: Write Good Control Store Parity
Bit 31 Clr: Write Good Tag Store Parity
Duplicate Tag Address x0000000000000000
MUX'ed Tag/Addr Field x0000000000000000
Partial Tag Field x0000000000000000
Duplicate Tag Test (R12) x80C0000880C00008
LOW LONGWORD Slice Follows
Bit 3 Set: TAG Control Parity Bit
Bit 31 Set: Dup Tag RAM, TAG Parity Bit
Dup Tag RAM, TAG Data x000000000000000C
HIGH LONGWORD Slice Follows
Bit 35 Set: TAG Control Parity Bit
Bit 63 Set: Dup Tag RAM, TAG Parity Bit
Dup Tag RAM, TAG Data x000000000000000C
Dup Tag Reserve Reg (R13) x0000000000000000
I-Bus Control Stat (R14) x0000100000001000
LOW LONGWORD Slice Follows
Bit 12 Set: Enable I-Bus Parity Check
HIGH LONGWORD Slice Follows
Bit 44 Set: Enable I-Bus Parity Check
I-Bus Error Addr Reg(R15) xFF2813C2000018A3
LOW LONGWORD Slice Follows
C-Bus<31:0> C/A Data x00000000000018A3
HIGH LONGWORD Slice Follows
C-Bus<63:32> C/A Data x00000000FF2813C2
Arbitration Ctrl Reg(R16) x0000012000000120
LOW LONGWORD Slice Follows
Bit 5 Set: C-Bus2 DONATE Mode Enabled
Bit 8 Set: C-Bus2 PAWN Mode Enabled
HIGH LONGWORD Slice Follows
Bit 37 Set: C-Bus2 DONATE Mode Enabled
Bit 40 Set: C-Bus2 PAWN Mode Enabled
C-Bus2 Control Reg (R17) x0000120100001201
LOW LONGWORD Slice Follows
Bit 0 Set: C-Bus2 Parity Checking Enabled
Bit 12 Set: Enable C-Bus2 Error Interrupt
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Parity Checking Enabled
CPU Cmdr ID Field: C-Bus2 CPU #1 ID
Bit 44 Set: Enable C-Bus2 Error Interrupt
C-Bus2 Error Reg (R18) x0000000000000000
C-Bus2 Err Addr Low (R19) xFF2813C2000018AB
LOW LONGWORD Slice Follows
CBus CAD<31:0> Er Adr x00000000000018AB
HIGH LONGWORD Slice Follows
CBus CAD<95:64> Er Adr x00000000FF2813C2
C-Bus2 Err Addr High(R20) x0F2013C3E00000B3
LOW LONGWORD Slice Follows
CBus CAD<63:32> Er Adr x00000000E00000B3
HIGH LONGWORD Slice Follows
CBus CAD<127:96> Er Adr x000000000F2013C3
C-Bus2 Reserve Reg (R21) x0000000000000000
Address Lock Reg (R22) x0072822100728221
LOW LONGWORD Slice Follows
Bit 0 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000039411
HIGH LONGWORD Slice Follows
Bit 32 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000039411
Proc Mailbox Reg (R23) x0000000000000000
Inter-Proc Int Req (R24) x0000000000000000
System Int Clear Reg(R25) x0000000000000000
Perf Monitor Ctl Reg(R26) x0000000000000000
Perf Monitor Reg 1 (R27) x0000000000000000
Perf Monitor Reg 2 (R28) x0000000000000000
Perf Monitor Reg 3 (R29) x0000000000000000
Perf Monitor Reg 4 (R30) x0000000000000000
Perf Monitor Reg 5 (R31) x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE000005230485D0
Bit 4 Set: PCI Slot 0 Present
Bit 6 Set: PCI Interrupt Detected
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 10 Set: EV5 Exclusive Exchange Enabled
Bit 15 Set: PCI Slot 2 Present
Bit 18 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 29 Set: CBUS Parity Checking Enabled
Bit 32 Set: CBUS Back-to-Back Cycles Enbld
T2 Revision: Pass 3
State Machine Vis Select: CBUS Cyc Counter
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter Enabled
Bit 59 Set: PCI SERR# Interrupts Enabled
Bit 60 Set: PCI PERR# Interrupts Enabled
Bit 61 Set: PCI Rd Data Prty Inter Enabled
Bit 62 Set: PCI Adr Parity Inter Enabled
Bit 63 Set: PCI Wrt Data Prty Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000000000
CERR2 Failed C/A <63:00> x000C0D38000C0D38
CERR3 Failed C/A <127:64> xF0405B33F0405B33
PERR1 PCI Error Reg 1 x0000000000000002
Bit 1 Set: PCI Address Parity Error
PERR2 PCI Cmd & Err Addr x0000000011B59F8A
Failed Cmd & Addr Valid When Parity Error
Failed PCI Cmd: x0 Interrupt Acknowledge
PCI Error Address: x0000000011B59F8A
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD <31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x000000000010603F
PC Hole End Addr: x000000000000003F
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x0000000000000000
PCI Window End Adr: x0000000000000000
PCI Window Start Adr: x0000000000000000
WMASK1 Window Mask Reg 1 x0000000000000000
PCI Window Mask: x0000000000000000
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr: x0000000000000000
WBASE2 Window Base Reg 2 x00000000000C03FF
PCI Window End Adr: x00000000000003FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000000
WMASK2 Window Mask Reg 2 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE2 Translated Base R2 x0000000000500000
Translated Base Addr: x0000000000002800
TDR0 TLB Data Register 0 x000000000005FDFF
TDR0 Data is Invalid
TLB Entry 0 Tag Data x000000000005FDFF
TLB Entry 0 PFN Data x0000000000000000
TDR1 TLB Data Register 1 x0000002400000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data x0000000000000000
TLB Entry 1 PFN Data x0000000000000012
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data x0000000000000000
TLB Entry 2 PFN Data x0000000000000000
TDR3 TLB Data Register 3 x0000000000000003
TDR3 Data is Invalid
TLB Entry 3 Tag Data x0000000000000003
TLB Entry 3 PFN Data x0000000000000000
TDR4 TLB Data Register 4 x0000000000000000
TDR4 Data is Invalid
TLB Entry 4 Tag Data x0000000000000000
TLB Entry 4 PFN Data x0000000000000000
TDR5 TLB Data Register 5 x0000000000000000
TDR5 Data is Invalid
TLB Entry 5 Tag Data x0000000000000000
TLB Entry 5 PFN Data x0000000000000000
TDR6 TLB Data Register 6 x0000000000000000
TDR6 Data is Invalid
TLB Entry 6 Tag Data x0000000000000000
TLB Entry 6 PFN Data x0000000000000000
TDR7 TLB Data Register 7 x0000000000000000
TDR7 Data is Invalid
TLB Entry 7 Tag Data x0000000000000000
TLB Entry 7 PFN Data x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x0000000000000000
Command Trap Register 1 xE2000008E2000008
Command Trap Register 2 x00400FF740400FF7
Configuration Register x8005506880055068
EDC Status Register 1 x08D70C140D5D0C14
[Even] Read CBITS <11:0> x0000000000000C14
[Even] Write CBITS <11:0> x0000000000000D5D
[Odd] Read CBITS <11:0> x0000000000000C14
[Odd] Write CBITS <11:0> x00000000000008D7
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
Error Register 1 x0000000000000000
Command Trap Register 1 xE2400008E2400008
Command Trap Register 2 x00400FF740400FF7
Configuration Register x8015506980155069
EDC Status Register 1 x000A0833000A0833
[Even] Read CBITS <11:0> x0000000000000833
[Even] Write CBITS <11:0> x000000000000000A
[Odd] Read CBITS <11:0> x0000000000000833
[Odd] Write CBITS <11:0> x000000000000000A
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
Error Register 1 x0000000000000000
Command Trap Register 1 xE2800008E2800008
Command Trap Register 2 x004000F7404000F7
Configuration Register x9001506A9001506A
EDC Status Register 1 x05390C140ABA0C14
[Even] Read CBITS <11:0> x0000000000000C14
[Even] Write CBITS <11:0> x0000000000000ABA
[Odd] Read CBITS <11:0> x0000000000000C14
[Odd] Write CBITS <11:0> x0000000000000539
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000003
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
******************************** ENTRY 4 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 2.
Timestamp of occurrence 18-FEB-1997 15:54:22
Host name stfep2
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000003
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000022 Machine Check Frame
CPU Number Logging Event 0.
- ALPHA EV5 COMMON REGS -
Flags: x00000000
Machine Check Error Code x00000202 CPU Detected Unrecoverable Error
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x0000000000000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 xFFFFFFFFAF4FC000
PALTEMP1 x0000000000000000
PALTEMP2 xFFFFFC00004E10F0
PALTEMP3 x0000000000004200
PALTEMP4 x0000000000000003
PALTEMP5 x0000000000000000
PALTEMP6 x000000000016658E
PALTEMP7 xFFFFFC00004E0B70
PALTEMP8 x1F1E161514020100
PALTEMP9 xFFFFFC00004E0E60
PALTEMP10 xFFFFFC000039A668
PALTEMP11 xFFFFFC00004E0CC0
PALTEMP12 xFFFFFC00004E1060
PALTEMP13 x0000012000000120
PALTEMP14 x0000000000000001
PALTEMP15 x0000000000000000
PALTEMP16 x0000020306600001
PALTEMP17 x0000000000000000
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFFAF4FF978
PALTEMP20 x0000000000940000
PALTEMP21 xFFFFFC00004E1090
PALTEMP22 xFFFFFC00006D72B0
PALTEMP23 x000000005FBE3A58
Exception Address Reg xFFFFFC000039A668
Native-mode Instruction
Exception PC x3FFFFF00000E699A
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode: x0000000000000005
Interrupt Summary Reg x0000000000100000
External HW Interrupt at IPL20
AST Requests 3-0: x0000000000000000
IBOX Ctrl and Status Reg x0000004160800000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFFAF4FFD38
Memory Mgmt Flt Sts Reg x00000000000166D1
If Error, Reference Which Caused Was Write
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field: x000000000000001B
Fault Inst Opcode: x000000000000002C
Scache Address Reg xFFFFFF000001916F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF80140F6FFF
Last Bcache Access Resulted in a Miss.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is Set.
Value of Tag Control Shared Bit is Clear.
Value of Tag Control Valid Bit is Set.
Value of Parity Bit Covering Tag Store
Address Bits is Set.
Tag Address<38:20> Is: x0000000000000140
Ext Interface Address Reg xFFFFFF839020001F
Fill Syndrome Reg x0000000000000007
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF0000755A2F
- SYSTEM SPECIFIC REGS -
Configuration Reg (R0) x380003F238000002
LOW LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 12 Clr: Cmd/Data NOACK are Errors
Bit 24 Clr: IDLEBC Assert in Last Cycle 4
Bit 25 Clr: IDLEBC Assert During Cycle 4
Bit 27 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
HIGH LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 36 Set: Rx IPL31 on CBus CERR Assert
Bit 37 Set: Rx HALT on CBus SYS_EVENT
Bit 38 Set: Rx HALT on IIRR CSR24 HALT Req
Bit 39 Set: Rx INTERPROC INT on Write to
IIRR CSR24 INTERPROC INT Req
Bit 40 Set: Enable CIRQ<0> INT From T2
Bit 41 Set: Enable CIRQ<1> INT From XIO
Bit 44 Clr: Cmd/Data NOACK are Errors
Bit 56 Clr: IDLEBC Assert in Last Cycle 4
Bit 57 Clr: IDLEBC Assert During Cycle 4
Bit 59 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
Error Summary Reg (R1) x0000000000000000
EVB Control Register (R2) x0000006100000061
LOW LONGWORD Slice Follows
Bit 0 Set: Enable Addr-Cmd Parity Checking
Bit 5 Set: Enable Bcache ECC Corr QW0/QW2
Bit 6 Set: Enable ECC Check - QW0/QW2 Data
HIGH LONGWORD Slice Follows
Bit 32 Set: Enable Addr-Cmd Parity Check
Bit 37 Set: Enable Bcache ECC Corr QW1/QW3
Bit 38 Set: Enable ECC Check-QW1/QW3 Data
Victim Error Addr (R3) x013C0006013C0006
LOW LONGWORD Slice Follows
EVB<33:4> Victim Addr x00000000013C0006
HIGH LONGWORD Slice Follows
EVB<33:4> Victim Addr x00000000013C0006
Correctable Err Reg (R4) x0000000000000000
LOW LONGWORD Slice Follows
QW0 ECC Syndrome: No Syndrome Bits Set
QW2 ECC Syndrome: No Syndrome Bits Set
HIGH LONGWORD Slice Follows
QW1 ECC Syndrome: No Syndrome Bits Set
QW3 ECC Syndrome: No Syndrome Bits Set
Correctable Err Addr (R5) xB800000AB800000A
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
Uncorrectable Error (R6) x8000000080000000
LOW LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW0 Uncorr ECC Syndrome x0000000000000000
QW2 Uncorr ECC Syndrome x0000000000000000
HIGH LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW1 Uncorr ECC Syndrome x0000000000000000
QW3 Uncorr ECC Syndrome x0000000000000000
Uncorrectable Err Adr(R7) xB800000EB800000E
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
EVB Reserve Register (R8) x0000000000000000
Duplicate Tag Control(R9) x0000011100000111
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Enable
Bit 4 Set: Enable Tag Ctrl Parity Checking
Bit 8 Set: Enable Tag Parity Checking
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Enable
Bit 36 Set: Enable Tag Ctl Parity Checking
Bit 40 Set: Enable Tag Parity Checking
Duplicate Tag Error (R10) x0000000000006A40
LOW LONGWORD Slice Follows
Dup Tag Store Err Adr x0000000000000352
Dup Tag Test Control(R11) x0000000000000000
LOW LONGWORD Slice Follows
Bit 3 Clr: Write Good Control Store Parity
Bit 31 Clr: Write Good Tag Store Parity
Duplicate Tag Address x0000000000000000
MUX'ed Tag/Addr Field x0000000000000000
Partial Tag Field x0000000000000000
Duplicate Tag Test (R12) x1280000D1280000D
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Dirty Bit
Bit 2 Set: Duplicate Tag Valid Bit
Bit 3 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x0000000000000128
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Dirty Bit
Bit 34 Set: Duplicate Tag Valid Bit
Bit 35 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x0000000000000128
Dup Tag Reserve Reg (R13) x0000000000000000
I-Bus Control Stat (R14) x0000100000001000
LOW LONGWORD Slice Follows
Bit 12 Set: Enable I-Bus Parity Check
HIGH LONGWORD Slice Follows
Bit 44 Set: Enable I-Bus Parity Check
I-Bus Error Addr Reg(R15) x4F6012C3E0800073
LOW LONGWORD Slice Follows
C-Bus<31:0> C/A Data x00000000E0800073
HIGH LONGWORD Slice Follows
C-Bus<63:32> C/A Data x000000004F6012C3
Arbitration Ctrl Reg(R16) x0000012000000120
LOW LONGWORD Slice Follows
Bit 5 Set: C-Bus2 DONATE Mode Enabled
Bit 8 Set: C-Bus2 PAWN Mode Enabled
HIGH LONGWORD Slice Follows
Bit 37 Set: C-Bus2 DONATE Mode Enabled
Bit 40 Set: C-Bus2 PAWN Mode Enabled
C-Bus2 Control Reg (R17) x0000110100001001
LOW LONGWORD Slice Follows
Bit 0 Set: C-Bus2 Parity Checking Enabled
Bit 12 Set: Enable C-Bus2 Error Interrupt
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Parity Checking Enabled
CPU Cmdr ID Field: C-Bus2 CPU #0 ID
Bit 44 Set: Enable C-Bus2 Error Interrupt
C-Bus2 Error Reg (R18) x0000000000000000
C-Bus2 Err Addr Low (R19) x4F6012C3E0800093
LOW LONGWORD Slice Follows
CBus CAD<31:0> Er Adr x00000000E0800093
HIGH LONGWORD Slice Follows
CBus CAD<95:64> Er Adr x000000004F6012C3
C-Bus2 Err Addr High(R20) x0F6012C3E080009B
LOW LONGWORD Slice Follows
CBus CAD<63:32> Er Adr x00000000E080009B
HIGH LONGWORD Slice Follows
CBus CAD<127:96> Er Adr x000000000F6012C3
C-Bus2 Reserve Reg (R21) x0000000000000000
Address Lock Reg (R22) x00755A2100755A21
LOW LONGWORD Slice Follows
Bit 0 Set: Lock Address Field Valid
EV<30:5> Lock Address x000000000003AAD1
HIGH LONGWORD Slice Follows
Bit 32 Set: Lock Address Field Valid
EV<30:5> Lock Address x000000000003AAD1
Proc Mailbox Reg (R23) x0000000000000000
Inter-Proc Int Req (R24) x0000000000000000
System Int Clear Reg(R25) x0010000000000000
HIGH LONGWORD Slice Follows
Bit 52 Set: State of CIRQ<0> from T2
Perf Monitor Ctl Reg(R26) x0000000000000000
Perf Monitor Reg 1 (R27) x0000000000000000
Perf Monitor Reg 2 (R28) x0000000000000000
Perf Monitor Reg 3 (R29) x0000000000000000
Perf Monitor Reg 4 (R30) x0000000000000000
Perf Monitor Reg 5 (R31) x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE000005230485D0
Bit 4 Set: PCI Slot 0 Present
Bit 6 Set: PCI Interrupt Detected
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 10 Set: EV5 Exclusive Exchange Enabled
Bit 15 Set: PCI Slot 2 Present
Bit 18 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 29 Set: CBUS Parity Checking Enabled
Bit 32 Set: CBUS Back-to-Back Cycles Enbld
T2 Revision: Pass 3
State Machine Vis Select: CBUS Cyc Counter
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter Enabled
Bit 59 Set: PCI SERR# Interrupts Enabled
Bit 60 Set: PCI PERR# Interrupts Enabled
Bit 61 Set: PCI Rd Data Prty Inter Enabled
Bit 62 Set: PCI Adr Parity Inter Enabled
Bit 63 Set: PCI Wrt Data Prty Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000000000
CERR2 Failed C/A <63:00> x000C0D38000C0D38
CERR3 Failed C/A <127:64> xF0405B33F0405B33
PERR1 PCI Error Reg 1 x0000000000000002
Bit 1 Set: PCI Address Parity Error
PERR2 PCI Cmd & Err Addr x0000000011B59F8A
Failed Cmd & Addr Valid When Parity Error
Failed PCI Cmd: x0 Interrupt Acknowledge
PCI Error Address: x0000000011B59F8A
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD <31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x000000000010603F
PC Hole End Addr: x000000000000003F
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x0000000000000000
PCI Window End Adr: x0000000000000000
PCI Window Start Adr: x0000000000000000
WMASK1 Window Mask Reg 1 x0000000000000000
PCI Window Mask: x0000000000000000
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr: x0000000000000000
WBASE2 Window Base Reg 2 x00000000000C03FF
PCI Window End Adr: x00000000000003FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000000
WMASK2 Window Mask Reg 2 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE2 Translated Base R2 x0000000000500000
Translated Base Addr: x0000000000002800
TDR0 TLB Data Register 0 x000000000005FDFF
TDR0 Data is Invalid
TLB Entry 0 Tag Data x000000000005FDFF
TLB Entry 0 PFN Data x0000000000000000
TDR1 TLB Data Register 1 x0000002400000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data x0000000000000000
TLB Entry 1 PFN Data x0000000000000012
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data x0000000000000000
TLB Entry 2 PFN Data x0000000000000000
TDR3 TLB Data Register 3 x0000000000000003
TDR3 Data is Invalid
TLB Entry 3 Tag Data x0000000000000003
TLB Entry 3 PFN Data x0000000000000000
TDR4 TLB Data Register 4 x0000000000000000
TDR4 Data is Invalid
TLB Entry 4 Tag Data x0000000000000000
TLB Entry 4 PFN Data x0000000000000000
TDR5 TLB Data Register 5 x0000000000000000
TDR5 Data is Invalid
TLB Entry 5 Tag Data x0000000000000000
TLB Entry 5 PFN Data x0000000000000000
TDR6 TLB Data Register 6 x0000000000000000
TDR6 Data is Invalid
TLB Entry 6 Tag Data x0000000000000000
TLB Entry 6 PFN Data x0000000000000000
TDR7 TLB Data Register 7 x0000000000000000
TDR7 Data is Invalid
TLB Entry 7 Tag Data x0000000000000000
TLB Entry 7 PFN Data x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x0000000000000000
Command Trap Register 1 xE2000008E2000008
Command Trap Register 2 x002010B7402010B7
Configuration Register x8005506880055068
EDC Status Register 1 x08330ABE08330D54
[Even] Read CBITS <11:0> x0000000000000D54
[Even] Write CBITS <11:0> x0000000000000833
[Odd] Read CBITS <11:0> x0000000000000ABE
[Odd] Write CBITS <11:0> x0000000000000833
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
Error Register 1 x0000000000000000
Command Trap Register 1 xE2400008E2400008
Command Trap Register 2 x002000F7402000F7
Configuration Register x8015506980155069
EDC Status Register 1 x000A0833000A0833
[Even] Read CBITS <11:0> x0000000000000833
[Even] Write CBITS <11:0> x000000000000000A
[Odd] Read CBITS <11:0> x0000000000000833
[Odd] Write CBITS <11:0> x000000000000000A
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
Error Register 1 x0000000000000000
Command Trap Register 1 xE2800008E2800008
Command Trap Register 2 x002000F7402000F7
Configuration Register x9001506A9001506A
EDC Status Register 1 x05390C140ABA0C14
[Even] Read CBITS <11:0> x0000000000000C14
[Even] Write CBITS <11:0> x0000000000000ABA
[Odd] Read CBITS <11:0> x0000000000000C14
[Odd] Write CBITS <11:0> x0000000000000539
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000003
NULL Memory Frame. The registers in this
frame contain zeros
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 2523.1 | 2100RM pci parity errors write/address | CSC32::HUTMACHER | | Tue Feb 18 1997 08:37 | 29 |
| Hi Jotaro
similar notes in this notes file 2513, 2517, 1909 for reference
Since this is a alphaserver2100 and a Rackmount then problem
is likely the cpu backplane. this is where the t2 bridge chip
lives on a rackmount system and we have been seeing alot of
rackmounts systems crashing with pci write parity errors .or.
pci address parity errors intermittently.
ends up that some cbus cpu backplanes rev C03 have noisey pci
address lines. the newer rev C04 or higher rev 54-22601-01 have
a capacitor fco installed on them and cures this problem.
jim hutmacher mvhs colorado csc 800-354-9000 ext 25561
from T2 System-Bus to PCI Bridge Frame
PERR1 PCI Error Reg 1 x0000000000000002
Bit 1 Set: PCI Address Parity Error
this is bad address sometimes
bit21 set when it should not be
but not always other bits are
involved.
|
PERR2 PCI Cmd & Err Addr x0000000011B59F8A
Failed Cmd & Addr Valid When Parity Error
|
| 2523.2 | Domo-arigato | TKTVFS::IKEDA_J | ZOSO | Wed Feb 19 1997 06:45 | 5 |
| Jim-san
Thank you very much for your quick reply.
/ji
|