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| Title: | SABLE SYSTEM PUBLIC DISCUSSION |
|
| Moderator: | COSMIC::PETERSON |
|
| Created: | Mon Jan 11 1993 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 2614 |
| Total number of notes: | 10244 |
2520.0. "decevent 2.3 and memory 660 errors - whats a normal reporting rate?" by CX3PST::CSC32::J_BECKER (There's no substitute for a good boot) Thu Feb 13 1997 15:41
DECEVENT 2.3 is causing my customer (and me) some grief in the number
of mail messages they get for HARD ECC Errors (660). The problem
does not appear to be hard but correctable. We do get many of
them in a week. The customer has over ~30 5/250 systems and all
report these errors.
My questions are:
1) What are acceptable thresholds for errors on memory? How many
per day, per week, per month is acceptable for this system design?
The systems do not crash but we want to predict when to swap the
memory. No application interruption has happened and can
be tolorated. We want to set DECEVENT reporting thresholds to
this value. Currently, the threshold is set to 1 in 24 hours (ie
any occurance). Setting this to a reasonable value will help me
to know when a real problem is occuring and dial in to diagnose.
I am getting too many false alarms!
2) Why are they reported as Hard ECC (Entry Type) when in fact
they are correctable (Error Register 1 reports EDC Corr Error)?
Along this line, why doesn't the sysloa filter these unless
they are uncorrectable or exceed some threshold?
Below is an example mail and typical error record. This system has
logged 24 in the last 12 months. 30systems * 24 errors represents
720 mail messages in a year or 13 per week. This is a lot of
dialins that turn out to be no problems!!!
thanks
john becker
From: DIA$MANAGER
To: FSE
CC:
Subj: DECevent Diagnosis Information
DECevent Notification Report
DECevent has detected that the following device needs attention:
DEVICE: AUS7 AlphaSrv_2x00_EV5
NODE: AUS7
SYSTEM SERIAL NUMBER: 1234
SYSTEM TYPE: ALPHASERVER 2100 5 / 250
DECevent Diagnosis Information
Digital Services
Device: AUS7 AlphaSrv_2x00_EV5
Error: HARD
Count: 1
Theory: 8032C.011-1:2;99,1:1;99,2:5;99,2 8032C.011-1:2;99,1:1;99,2:
Evidence: TBD
Time Of Error: 96-05-02 02:08:58
******************************** ENTRY 4520 ********************************
Logging OS 1. OpenVMS
System Architecture 2. Alpha
OS version V6.2
Event sequence number 26451.
Timestamp of occurrence 06-MAY-1996 07:32:21
Time since reboot 4 Day(s) 5:26:35
Host name AUS7
System Model AlphaServer 2100 5/250
Entry type 8. Hard ECC Error
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000022 Machine Check Frame
CPU Number Logging Event 0.
- ALPHA EV5 COMMON REGS -
Flags: x00000000
Machine Check Error Code x00000202 CPU Detected Unrecoverable Error
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x0000000000000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 x000000000000004D
PALTEMP1 x000000007FEA08E0
PALTEMP2 xFFFFFFFF89E3CD18
PALTEMP3 x0000000000004200
PALTEMP4 x0000000000000000
PALTEMP5 x000000007FEA0900
PALTEMP6 x0000000000000001
PALTEMP7 x0000000000000003
PALTEMP8 x0000000000000004
PALTEMP9 x0000000000000003
PALTEMP10 xFFFFFFFF80620960
PALTEMP11 x0000000000000000
PALTEMP12 xFFFFFFFF81A70A00
PALTEMP13 x0000012000000120
PALTEMP14 x0000000000000001
PALTEMP15 x0000000000000000
PALTEMP16 x0000020206600001
PALTEMP17 x000052F67C055985
PALTEMP18 xFFFFFFFF80E10000
PALTEMP19 x000000007FF92000
PALTEMP20 x00000000340AE000
PALTEMP21 x0000000200000000
PALTEMP22 x0000000000A00000
PALTEMP23 x000000000BC9E080
Exception Address Reg xFFFFFFFF80620960
Native-mode Instruction
Exception PC x3FFFFFFFE0188258
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000008000
Base Addr for PALcode: x0000000000000002
Interrupt Summary Reg x0000000000000000
AST Requests 3-0: x0000000000000000
IBOX Ctrl and Status Reg x0000004144800000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instr's May be Issued.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg x000000007FEC3C14
Memory Mgmt Flt Sts Reg x0000000000014710
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field: x000000000000001C
Fault Inst Opcode: x0000000000000028
Scache Address Reg xFFFFFF000D01FE2F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF80008DAFFF
Last Bcache Access Resulted in a Miss.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is Clear.
Value of Tag Control Shared Bit is Set.
Value of Tag Control Valid Bit is Set.
Value of Parity Bit Covering Tag Store
Address Bits is Clear.
Tag Address<38:20> Is: x0000000000000008
Ext Interface Address Reg xFFFFFF839400001F
Fill Syndrome Reg x0000000000000007
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF001CA9C09F
- SYSTEM SPECIFIC REGS -
Configuration Reg (R0) x380013F238001002
LOW LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 12 Set: Cmd/Data NOACK are not Errors
Bit 24 Clr: IDLEBC Assert in Last Cycle 4
Bit 25 Clr: IDLEBC Assert During Cycle 4
Bit 27 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
HIGH LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 36 Set: Rx IPL31 on CBus CERR Assert
Bit 37 Set: Rx HALT on CBus SYS_EVENT
Bit 38 Set: Rx HALT on IIRR CSR24 HALT Req
Bit 39 Set: Rx INTERPROC INT on Write to
IIRR CSR24 INTERPROC INT Req
Bit 40 Set: Enable CIRQ<0> INT From T2
Bit 41 Set: Enable CIRQ<1> INT From XIO
Bit 44 Set: Cmd/Data NOACK are not Errors
Bit 56 Clr: IDLEBC Assert in Last Cycle 4
Bit 57 Clr: IDLEBC Assert During Cycle 4
Bit 59 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
Error Summary Reg (R1) x0000000000000000
EVB Control Register (R2) x000000E100000061
LOW LONGWORD Slice Follows
Bit 0 Set: Enable Addr-Cmd Parity Checking
Bit 5 Set: Enable Bcache ECC Corr QW0/QW2
Bit 6 Set: Enable ECC Check - QW0/QW2 Data
HIGH LONGWORD Slice Follows
Bit 32 Set: Enable Addr-Cmd Parity Check
Bit 37 Set: Enable Bcache ECC Corr QW1/QW3
Bit 38 Set: Enable ECC Check-QW1/QW3 Data
Bit 39 Set: Disable ECC Check on FILL Data
Victim Error Addr (R3) x0500000605000006
LOW LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000005000006
HIGH LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000005000006
Correctable Err Reg (R4) x0000000000000000
LOW LONGWORD Slice Follows
QW0 ECC Syndrome: No Syndrome Bits Set
QW2 ECC Syndrome: No Syndrome Bits Set
HIGH LONGWORD Slice Follows
QW1 ECC Syndrome: No Syndrome Bits Set
QW3 ECC Syndrome: No Syndrome Bits Set
Correctable Err Addr (R5) xB800000A00000622
LOW LONGWORD Slice Follows
Bit 32 Clr: EV-Bus Bit 39, IO Bit, Clr
EVB<34:4> Corr Err Adr x0000000000000622
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
Uncorrectable Error (R6) x8000000080000000
LOW LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW0 Uncorr ECC Syndrome x0000000000000000
QW2 Uncorr ECC Syndrome x0000000000000000
HIGH LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW1 Uncorr ECC Syndrome x0000000000000000
QW3 Uncorr ECC Syndrome x0000000000000000
Uncorrectable Err Adr(R7) xB800000EB800000E
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
EVB Reserve Register (R8) x0000000000000000
Duplicate Tag Control(R9) x0000011100000111
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Enable
Bit 4 Set: Enable Tag Ctrl Parity Checking
Bit 8 Set: Enable Tag Parity Checking
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Enable
Bit 36 Set: Enable Tag Ctl Parity Checking
Bit 40 Set: Enable Tag Parity Checking
Duplicate Tag Error (R10) x0000000000000100
LOW LONGWORD Slice Follows
Dup Tag Store Err Adr x0000000000000008
Dup Tag Test Control(R11) x0000000000000000
LOW LONGWORD Slice Follows
Bit 3 Clr: Write Good Control Store Parity
Bit 31 Clr: Write Good Tag Store Parity
Duplicate Tag Address x0000000000000000
MUX'ed Tag/Addr Field x0000000000000000
Partial Tag Field x0000000000000000
Duplicate Tag Test (R12) x0040000E0040000E
LOW LONGWORD Slice Follows
Bit 1 Set: Duplicate Tag Shared Bit
Bit 2 Set: Duplicate Tag Valid Bit
Bit 3 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x0000000000000004
HIGH LONGWORD Slice Follows
Bit 33 Set: Duplicate Tag Shared Bit
Bit 34 Set: Duplicate Tag Valid Bit
Bit 35 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x0000000000000004
Dup Tag Reserve Reg (R13) x0000000000000000
I-Bus Control Stat (R14) x0000100000001000
LOW LONGWORD Slice Follows
Bit 12 Set: Enable I-Bus Parity Check
HIGH LONGWORD Slice Follows
Bit 44 Set: Enable I-Bus Parity Check
I-Bus Error Addr Reg(R15) x4F400403E040006B
LOW LONGWORD Slice Follows
C-Bus<31:0> C/A Data x00000000E040006B
HIGH LONGWORD Slice Follows
C-Bus<63:32> C/A Data x000000004F400403
Arbitration Ctrl Reg(R16) x0000012000000120
LOW LONGWORD Slice Follows
Bit 5 Set: C-Bus2 DONATE Mode Enabled
Bit 8 Set: C-Bus2 PAWN Mode Enabled
HIGH LONGWORD Slice Follows
Bit 37 Set: C-Bus2 DONATE Mode Enabled
Bit 40 Set: C-Bus2 PAWN Mode Enabled
C-Bus2 Control Reg (R17) x0000110100001001
LOW LONGWORD Slice Follows
Bit 0 Set: C-Bus2 Parity Checking Enabled
Bit 12 Set: Enable C-Bus2 Error Interrupt
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Parity Checking Enabled
CPU Cmdr ID Field: C-Bus2 CPU #0 ID
Bit 44 Set: Enable C-Bus2 Error Interrupt
C-Bus2 Error Reg (R18) x0000000000000000
C-Bus2 Err Addr Low (R19) x4F400403E040008B
LOW LONGWORD Slice Follows
CBus CAD<31:0> Er Adr x00000000E040008B
HIGH LONGWORD Slice Follows
CBus CAD<95:64> Er Adr x000000004F400403
C-Bus2 Err Addr High(R20) x0F400403E0400093
LOW LONGWORD Slice Follows
CBus CAD<63:32> Er Adr x00000000E0400093
HIGH LONGWORD Slice Follows
CBus CAD<127:96> Er Adr x000000000F400403
C-Bus2 Reserve Reg (R21) x0000000000000000
Address Lock Reg (R22) x1CA9C0811CA9C081
LOW LONGWORD Slice Follows
Bit 0 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000E54E04
HIGH LONGWORD Slice Follows
Bit 32 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000E54E04
Proc Mailbox Reg (R23) x0000000000000000
Inter-Proc Int Req (R24) x0000000000000000
System Int Clear Reg(R25) x0000000000000000
Perf Monitor Ctl Reg(R26) x0000000000000000
Perf Monitor Reg 1 (R27) x0000000000000000
Perf Monitor Reg 2 (R28) x0000000000000000
Perf Monitor Reg 3 (R29) x0000000000000000
Perf Monitor Reg 4 (R30) x0000000000000000
Perf Monitor Reg 5 (R31) x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x0000000000000000
Command Trap Register 1 xE2000008E2000008
Command Trap Register 2 x0020014740200147
Configuration Register x8005506880055068
EDC Status Register 1 x0F62059C0E0804D2
[Even] Read CBITS <11:0> x00000000000004D2
[Even] Write CBITS <11:0> x0000000000000E08
[Odd] Read CBITS <11:0> x000000000000059C
[Odd] Write CBITS <11:0> x0000000000000F62
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
Error Register 1 x0004000100000000
[Odd] Error Summary
[Odd] EDC Corr Error
Command Trap Register 1 x06ACA128E2400008
Command Trap Register 2 xF048337240202FC7
Configuration Register x8015506980155069
EDC Status Register 1 x0C2B059D09400698
[Even] Read CBITS <11:0> x0000000000000698
[Even] Write CBITS <11:0> x0000000000000940
[Odd] Read CBITS <11:0> x000000000000059D
[Odd] Write CBITS <11:0> x0000000000000C2B
EDC Status Register 2 x000000260000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000026
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
Error Register 1 x0000000000000000
Command Trap Register 1 xE2800008E2800008
Command Trap Register 2 x00202FC740202FC7
Configuration Register x9001506A9001506A
EDC Status Register 1 x083303EE08330CD6
[Even] Read CBITS <11:0> x0000000000000CD6
[Even] Write CBITS <11:0> x0000000000000833
[Odd] Read CBITS <11:0> x00000000000003EE
[Odd] Write CBITS <11:0> x0000000000000833
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS < x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1 x0000000000000000
[Odd] Subs. Write CBITS < x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11: x00000000000000D8
[Odd] Syndrome Mask <11:0 x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11: x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0 x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE000005230005B0
Bit 4 Set: PCI Slot 0 Present
Bit 5 Set: PCI Slot 0 Present
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 10 Set: EV5 Exclusive Exchange Enabled
Bit 24 Set: NOACK, CUCERR, OutOfSync Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 29 Set: CBUS Parity Checking Enabled
Bit 32 Set: CBUS Back-to-Back Cycles Enbld
T2 Revision: Pass 3
State Machine Vis Select: CBUS Cyc Counter
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter Enabled
Bit 59 Set: PCI SERR# Interrupts Enabled
Bit 60 Set: PCI PERR# Interrupts Enabled
Bit 61 Set: PCI Rd Data Prty Inter Enabled
Bit 62 Set: PCI Adr Parity Inter Enabled
Bit 63 Set: PCI Wrt Data Prty Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000000000
CERR2 Failed C/A <63:00> xE3800010E3800010
CERR3 Failed C/A <127:64> x00202FC740202FC7
PERR1 PCI Error Reg 1 x0000000000000000
PERR2 PCI Cmd & Err Addr x0000000701000420
Failed Cmd & Addr Valid When Parity Error
Failed PCI Cmd: x7 Memory Write
PCI Error Address: x0000000001000420
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD <31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x00000000001060FF
PC Hole End Addr: x00000000000000FF
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x00000000000C03FF
PCI Window End Adr: x00000000000003FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000000
WMASK1 Window Mask Reg 1 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE1 Translated Base R1 x0000000001A00000
Translated Base Addr: x000000000000D000
WBASE2 Window Base Reg 2 x00000000400807FF
PCI Window End Adr: x00000000000007FF
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000400
WMASK2 Window Mask Reg 2 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE2 Translated Base R2 x0000000000000000
Translated Base Addr: x0000000000000000
TDR0 TLB Data Register 0 x0000000000000000
TDR0 Data is Invalid
TLB Entry 0 Tag Data x0000000000000000
TLB Entry 0 PFN Data x0000000000000000
TDR1 TLB Data Register 1 x0000000000000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data x0000000000000000
TLB Entry 1 PFN Data x0000000000000000
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data x0000000000000000
TLB Entry 2 PFN Data x0000000000000000
TDR3 TLB Data Register 3 x0000000000000000
TDR3 Data is Invalid
TLB Entry 3 Tag Data x0000000000000000
TLB Entry 3 PFN Data x0000000000000000
TDR4 TLB Data Register 4 x0000000000000000
TDR4 Data is Invalid
TLB Entry 4 Tag Data x0000000000000000
TLB Entry 4 PFN Data x0000000000000000
TDR5 TLB Data Register 5 x0000000000000000
TDR5 Data is Invalid
TLB Entry 5 Tag Data x0000000000000000
TLB Entry 5 PFN Data x0000000000000000
TDR6 TLB Data Register 6 x0000000000000000
TDR6 Data is Invalid
TLB Entry 6 Tag Data x0000000000000000
TLB Entry 6 PFN Data x0000000000000000
TDR7 TLB Data Register 7 x0000000000000000
TDR7 Data is Invalid
TLB Entry 7 Tag Data x0000000000000000
TLB Entry 7 PFN Data x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000010 PCI Frame
PCI Configuration Addr x0000004000000000
Target Slot or Device: 0.
Target Bus Number is: 0.
Device and Vendor ID x00021011 DECchip 21040 10MHz TULIP Ethernet Chip
Vendor ID: x1011 (Digital Equip Corp)
Device ID: x00000002
Command Register x0007 I/O Space Accesses Response: Enabled
Memory Space Accesses Response: Enabled
PCI Bus Master Capability: Enabled
Monitor for Special Cycle Ops: DISABLED
Generate Mem Wrt/Invalidate Cmds: DISABLED
Parity Error Detection Response: *IGNORE*
Wait Cycle Address/Data Stepping: DISABLED
SERR# Sys Err Driver Capability: DISABLED
Fast Back-to-Back to Many Target: DISABLED
Status Register x0280 Device is 33 Mhz Capable.
No Support for User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x23
Device Class Code x020000 Network Controller: Ethernet Controller
Sys Cache Line Size x00
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00010201
Base Address Register 2 x81000200
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x02
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
-- ENTRY FRAME FOLLOWS --
Frame ID x00000010 PCI Frame
PCI Configuration Addr x0000004000000800
Target Slot or Device: 1.
Target Bus Number is: 0.
Device and Vendor ID x00011000 NCR 53C810 NCR_810 SCSI Narrow SingleEnded
Vendor ID: x1000 (NCR)
Device ID: x00000001
Command Register x0007 I/O Space Accesses Response: Enabled
Memory Space Accesses Response: Enabled
PCI Bus Master Capability: Enabled
Monitor for Special Cycle Ops: DISABLED
Generate Mem Wrt/Invalidate Cmds: DISABLED
Parity Error Detection Response: *IGNORE*
Wait Cycle Address/Data Stepping: DISABLED
SERR# Sys Err Driver Capability: DISABLED
Fast Back-to-Back to Many Target: DISABLED
Status Register x0200 Device is 33 Mhz Capable.
No Support for User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Not Supported in Target Device.
Device Select Timing: Medium.
Device Revision x02
Device Class Code x010000 Mass Storage: SCSI Bus Controller
Sys Cache Line Size x00
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00010001
Base Address Register 2 x81000000
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x01
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
-- ENTRY FRAME FOLLOWS --
Frame ID x00000010 PCI Frame
PCI Configuration Addr x0000004000001000
Target Slot or Device: 2.
Target Bus Number is: 0.
Device and Vendor ID x04828086 Intel 82375EB ** PCI-to-EISA BRIDGE **
Vendor ID: x8086 (Intel)
Device ID: x00000482
Command Register x0007 I/O Space Accesses Response: Enabled
Memory Space Accesses Response: Enabled
PCI Bus Master Capability: Enabled
Monitor for Special Cycle Ops: DISABLED
Generate Mem Wrt/Invalidate Cmds: DISABLED
Parity Error Detection Response: *IGNORE*
Wait Cycle Address/Data Stepping: DISABLED
SERR# Sys Err Driver Capability: DISABLED
Fast Back-to-Back to Many Target: DISABLED
Status Register x0200 Device is 33 Mhz Capable.
No Support for User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Not Supported in Target Device.
Device Select Timing: Medium.
Device Revision x04
Device Class Code x000000 Zero's: Undefined or No Class Code Support
Sys Cache Line Size x00
Latency Timer Value xF8
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00000000
Base Address Register 2 x00000000
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x00
Interrupt Pin Being Used x00
Min Bus Grant/Burst x00
Max Bus Latency x00
-- ENTRY FRAME FOLLOWS --
Frame ID x00000010 PCI Frame
PCI Configuration Addr x0000004000003000
Target Slot or Device: 6.
Target Bus Number is: 0.
Device and Vendor ID x00011000 NCR 53C810 NCR_810 SCSI Narrow SingleEnded
Vendor ID: x1000 (NCR)
Device ID: x00000001
Command Register x0007 I/O Space Accesses Response: Enabled
Memory Space Accesses Response: Enabled
PCI Bus Master Capability: Enabled
Monitor for Special Cycle Ops: DISABLED
Generate Mem Wrt/Invalidate Cmds: DISABLED
Parity Error Detection Response: *IGNORE*
Wait Cycle Address/Data Stepping: DISABLED
SERR# Sys Err Driver Capability: DISABLED
Fast Back-to-Back to Many Target: DISABLED
Status Register x0200 Device is 33 Mhz Capable.
No Support for User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Not Supported in Target Device.
Device Select Timing: Medium.
Device Revision x01
Device Class Code x000000 Zero's: Undefined or No Class Code Support
Sys Cache Line Size x00
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00010101
Base Address Register 2 x81000100
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x00
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
-- ENTRY FRAME FOLLOWS --
Frame ID x00000012 EISA System Component (ESC) Frame
Revision ID Register x03
Mode Select Register x6B PIRQx# Mux/Map Ctrl<2:0>: x03
NMI on SERR(SysErr) Sig Enabled
GPCS[2:0]# Functions Selected
Config RAM Page Adr Gen Enabled
MREQ[7:4]#/PIRQ[3:0]# Enabled
EISA Motherboard ID-0 Reg x10
EISA Motherboard ID-1 Reg xA3
EISA Motherboard ID-2 Reg x2A
EISA Motherboard ID-3 Reg x01
Scatter-Gather Base Addr x04
PIRQ Route CSR-0 x6B IRQ Routing Bits <06:00>: Reserved IRQx
Routing of Interrupts Enabled
PIRQ Route CSR-1 x00 IRQ Routing Bits <06:00>: Reserved IRQx
Routing of Interrupts Enabled
PIRQ Route CSR-2 x00 IRQ Routing Bits <06:00>: Reserved IRQx
Routing of Interrupts Enabled
PIRQ Route CSR-3 x00 IRQ Routing Bits <06:00>: Reserved IRQx
Routing of Interrupts Enabled
NMI Status and Control x20 Sys Board Err(ERR) Sig Enabled
IOCHK# Sig NMI's are Enabled
NMI Extended Status/Ctrl x00 Software NMI Generation Disabled
NMI on FailSafe Timeout Disabled
NMI on EISA Bus Timeout Disabled
Current NMI Not By Bus Timeout
Current NMI Not By NMI Port Wrt
Last EISA Master Granted xEF Undefined Register Bit Configuration
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
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