| Title: | SABLE SYSTEM PUBLIC DISCUSSION |
| Moderator: | COSMIC::PETERSON |
| Created: | Mon Jan 11 1993 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 2614 |
| Total number of notes: | 10244 |
Hi!
Attached is an errorlog-entry (Decevent) from VMS on a SABLE
It is a T2-PCI Parity Error.
Is it possible to isolate the failing PCI-Card by these
Errorlog? If so can somebody help me?
Thanks in advance
Helmut
******************************** ENTRY 2
********************************
Logging OS 1. OpenVMS
System Architecture 2. Alpha
OS version V6.1
Event sequence number 9989.
Timestamp of occurrence 05-FEB-1997 10:42:18
Time since reboot 14 Day(s) 14:12:19
Host name COLDB1
System Model AlphaServer 2100 4/233
Entry type 2. Machine Check
CPU Minor class 1. Machine check (670 entry)
-- KERNEL EVENT HEADER --
Entry Byte Count x00000108
Error Log Frame Revision x0000
SCB Vector x0660 System Machine Check Abort
Severity x0000 Field Not Valid
CPU Number Logging Event 0.
Error Count x0002
Fail Code x0000 No Fail Code Loaded for This Event
Error Field 0 x0000000000000000
Error Field 1 x0000000000000100
T2 - PCI Write Data Parity Error
Error Field 2 x0000000000000000
Error Field 3 x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
Byte Count x000000B8
IO Control/Status Reg xFE000084270E81B0
Bit 4 Set: PCI Slot 0 Present
Bit 5 Set: PCI Slot 0 Present
Bit 7 Set: TLB Error Checking
Enabled
Bit 8 Set: CBUS CXACK Check
Enabled
Bit 15 Set: PCI Slot 2 Present
Bit 18 Set: PCI Slot 1 Present
Bit 19 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR,
OutOfSync Enbld
Bit 25 Set: PCI Memory Space
Enabled
Bit 26 Set: Translation Look-Aside
Enabled
Bit 29 Set: CBUS Parity Checking
Enabled
T2 Revision: Pass 3
State Machine Vis Select: CBUS Cyc
Counter
Bit 39 Set: PCI Slot 2 Present
Bit 57 Set: PCI NMI Interrupts
Enabled
Bit 58 Set: PCI Dev Timeout Inter
Enabled
Bit 59 Set: PCI SERR# Interrupts
Enabled
Bit 60 Set: PCI PERR# Interrupts
Enabled
Bit 61 Set: PCI Rd Data Prty Inter
Enabled
Bit 62 Set: PCI Adr Parity Inter
Enabled
Bit 63 Set: PCI Wrt Data Prty
Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000000000
CERR2 Failed C/A <63:00> xE8002990E8002990
CERR3 Failed C/A <127:64> x20200003E0200003
PERR1 PCI Error Reg 1 x0000000000000001
Bit 0 Set: PCI Write Data Parity
Error
PERR2 PCI Cmd & Err Addr x000000070A56C480
Failed Cmd & Addr Valid When
Parity Error
Failed PCI Cmd: x7 Memory Write
PCI Error Address:
x000000000A56C480
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD
<31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x0000000000106040
PC Hole End Addr:
x0000000000000040
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr:
x0000000000000020
WBASE1 Window Base Reg 1 x00000000000803FF
PCI Window End Adr:
x00000000000003FF
Bit 19 Set: PCI Window Enable
PCI Window Start Adr:
x0000000000000000
WMASK1 Window Mask Reg 1 x000000003FF00000
PCI Window Mask:
x00000000000003FF
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr:
x0000000000000000
WBASE2 Window Base Reg 2 x00000000400C047F
PCI Window End Adr:
x000000000000047F
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr:
x0000000000000400
WMASK2 Window Mask Reg 2 x0000000007F00000
PCI Window Mask:
x000000000000007F
TBASE2 Translated Base R2 x0000000000670000
Translated Base Addr:
x0000000000003380
TDR0 TLB Data Register 0 x0000256B0019C310
TLB Entry 0 Tag Data
x000000000019C310
TLB Entry 0 PFN Data
x00000000000012B5
TDR1 TLB Data Register 1 x00000EC50019C314
TLB Entry 1 Tag Data
x000000000019C314
TLB Entry 1 PFN Data
x0000000000000762
TDR2 TLB Data Register 2 x000026710019C058
TLB Entry 2 Tag Data
x000000000019C058
TLB Entry 2 PFN Data
x0000000000001338
TDR3 TLB Data Register 3 x000012A10019C000
TLB Entry 3 Tag Data
x000000000019C000
TLB Entry 3 PFN Data
x0000000000000950
TDR4 TLB Data Register 4 x0000022D0019C184
TLB Entry 4 Tag Data
x000000000019C184
TLB Entry 4 PFN Data
x0000000000000116
TDR5 TLB Data Register 5 x00001C650019C30C
TLB Entry 5 Tag Data
x000000000019C30C
TLB Entry 5 PFN Data
x0000000000000E32
TDR6 TLB Data Register 6 x0000022F0019C185
TLB Entry 6 Tag Data
x000000000019C185
TLB Entry 6 PFN Data
x0000000000000117
TDR7 TLB Data Register 7 x0000259D0019C05C
TLB Entry 7 Tag Data
x000000000019C05C
TLB Entry 7 PFN Data
x00000000000012CE
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
Byte Count x00000000
(sorry the format is not very well)
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 2513.1 | pci addr/write parity errors RM's | CSC32::HUTMACHER | Fri Feb 07 1997 16:21 | 12 | |
Hi Helmut
if this alphaserver2100 and is a Rackmount then problem is likely
the cpu backplane. this is where the t2 bridge chip lives on rackmount
system and we have been seeing alot of rackmounts systems crashing with
pci write parity errors .or. pci address parity errors intermittently.
ends up that some cbus cpu backplanes rev C03 have noisey pci address
lines. the newer rev C04 54-22601-01 have a capicator fco installed on
them and cures this problem.
jim hutmacher mvhs colorado csc 800-354-9000 ext 25561
| |||||
| 2513.2 | thank you Jim!! | ATZIS2::PUTZENLECHNE | wherever is fun, there's always ALPHA | Fri Feb 14 1997 09:23 | 2 |
TY
| |||||