| We have a customer running Unix 3.2C on an AlphaServer 2100 5/250. It has
been crashing intermittently about once a week. The foot print of the
crash is very similar to the one described in the base note. There is
nothing logged in the error registers except the "invalid PFN".
Any suggestions to troubleshoot the problem are welcome. We need all
the help we can get.
DECevent V2.1
******************************** ENTRY 1********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 0.
Timestamp of occurrence 28-MAY-1997 11:18:10
Host name hx23
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 300. Start-Up ASCII Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 3. Startup
ASCII Message
Alpha boot: available memory from 0x2ad2000 to 0x7fffe000
Digital UNIX V3.2C (Rev. 148); Fri Oct 18 15:41:18 EST 1996
physical memory = 2048.00 megabytes.
available memory = 2005.26 megabytes.
using 7856 buffers containing 61.37 megabytes of memory
Master cpu at slot 0.
Firmware revision: 4.3
PALcode: OSF version 1.18
ibus0 at nexus
AlphaServer 2100 5/250
cpu 0 EV-5 4mb b-cache
cpu 1 EV-5 4mb b-cache
gpc0 at ibus0
pci0 at ibus0 slot 0
tu0: DECchip 21040-AA: Revision: 2.3
tu0 at pci0 slot 0
tu0: DEC TULIP Ethernet Interface, hardware address:
08-00-2B-E5-C0-4B
tu0: console mode: selecting UTP (10BaseT) port: no link
psiop0 at pci0 slot 1
Loading SIOP: script 10cc300, reg 81125000, data 10d8300
scsi0 at psiop0 slot 0
rz0 at scsi0 bus 0 target 0 lun 0 (DEC RZ28M (C) DEC 0466)
rz1 at scsi0 bus 0 target 1 lun 0 (DEC RZ28M (C) DEC 0568)
rz5 at scsi0 bus 0 target 5 lun 0 (DEC RRD43 (C) DEC 1084)
eisa0 at pci0
ace0 at eisa0
ace1 at eisa0
lp0 at eisa0
fdi0 at eisa0
fd0 at fdi0 unit 0
vga0 at eisa0
1024x768 (QVision )
pza0 at pci0 slot 6
pza0 firmware version: DEC P01 A10
scsi1 at pza0 slot 0
rz8 at scsi1 bus 1 target 0 lun 0 (DEC HSZ50-AX V50Z)
rz9 at scsi1 bus 1 target 1 lun 0 (DEC HSZ50-AX V50Z)
rz9 at scsi1 bus 1 target 1 lun 1 (DEC HSZ50-AX V50Z)
rz9 at scsi1 bus 1 target 1 lun 2 (DEC HSZ50-AX V50Z)
tz13 at scsi1 bus 1 target 5 lun 0 (DEC TZ887 (C) DEC CC33)
fta0 DEC DEFPA FDDI Module, Hardware Revision 0
fta0 at pci0 slot 7
fta0: DMA Available.
fta0: DEC DEFPA (PDQ) FDDI Interface, Hardware address:08-00-2B-B3-E2-FE
fta0: Firmware rev: 2.46
Initializing xcr0. Please wait.
Initializing xcr0. Please wait.
Initializing xcr0. Please wait.
Initializing xcr0. Please wait.
xcr0 at pci0 slot 8
re0 at xcr0 unit 0 (unit status = ONLINE, raid level = JBOD)
re1 at xcr0 unit 1 (unit status = ONLINE, raid level = JBOD)
re2 at xcr0 unit 2 (unit status = ONLINE, raid level = JBOD)
re3 at xcr0 unit 3 (unit status = ONLINE, raid level = 5)
lvm0: configured.
lvm1: configured.
dli: configured
SuperLAT. Copyright 1993 Meridian Technology Corp. All rights
reserved.
******************************** ENTRY 2********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 3.
Timestamp of occurrence 28-MAY-1997 10:57:15
Host name hx23
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000002
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 302. ASCII Panic Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 1. Panic
ASCII Message panic (cpu 0): System Uncorrectable
Machine Check 660
******************************** ENTRY 3********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 2.
Timestamp of occurrence 28-MAY-1997 10:57:15
Host name hx23
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000002
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000022 Machine Check Frame
CPU Number Logging Event 0.
- ALPHA EV5 COMMON REGS -
Flags: x00000000
Machine Check Error Code x00000202 CPU Detected Unrecoverable Error
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x0000000000000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 x0000000000000241
PALTEMP1 x0000000000000241
PALTEMP2 xFFFFFC00004DCFA0
PALTEMP3 x0000000000004200
PALTEMP4 x0000000000000000
PALTEMP5 x0000000000000000
PALTEMP6 xFFFFFC0073E1B188
PALTEMP7 xFFFFFC00004DCA20
PALTEMP8 x1F1E161514020100
PALTEMP9 xFFFFFC00004DCD10
PALTEMP10 xFFFFFC0000400364
PALTEMP11 xFFFFFC00004DCB70
PALTEMP12 xFFFFFC00004DCF10
PALTEMP13 x0000012000000120
PALTEMP14 x0000000000000001
PALTEMP15 x0000000000000000
PALTEMP16 x0000020306600001
PALTEMP17 x0000000000000000
PALTEMP18 x000000011FFFFBF0
PALTEMP19 xFFFFFFFFB78B2DD0
PALTEMP20 x000000001B57A000
PALTEMP21 xFFFFFC00004DCF40
PALTEMP22 xFFFFFC0000671320
PALTEMP23 x0000000074E4FA58
Exception Address Reg xFFFFFC0000400364
Native-mode Instruction
Exception PC x3FFFFF00001000D9
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode:x0000000000000005
Interrupt Summary Reg x0000000000000000
AST Requests 3-0:x0000000000000000
IBOX Ctrl and Status Reg x0000004160800000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFFB69CD8D8
Memory Mgmt Flt Sts Reg x0000000000014E50
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field:x0000000000000019
Fault Inst Opcode:x0000000000000029
Scache Address Reg xFFFFFF000001916F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF802ECF6FFF
Last Bcache Access Resulted in a Miss.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is Set.
Value of Tag Control Shared Bit is Clear.
Value of Tag Control Valid Bit is Set.
Value of Parity Bit Covering Tag Store
Address Bits is Set.
Tag Address<38:20> Is:x00000000000002EC
Ext Interface Address Reg xFFFFFF839020001F
Fill Syndrome Reg x0000000000000007
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF00006DDB4F
- SYSTEM SPECIFIC REGS -
Configuration Reg (R0) x380003F238000002
LOW LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 12 Clr: Cmd/Data NOACK are Errors
Bit 24 Clr: IDLEBC Assert in Last Cycle 4
Bit 25 Clr: IDLEBC Assert During Cycle 4
Bit 27 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
HIGH LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 36 Set: Rx IPL31 on CBus CERR Assert
Bit 37 Set: Rx HALT on CBus SYS_EVENT
Bit 38 Set: Rx HALT on IIRR CSR24 HALT Req
Bit 39 Set: Rx INTERPROC INT on Write to
IIRR CSR24 INTERPROC INT Req
Bit 40 Set: Enable CIRQ<0> INT From T2
Bit 41 Set: Enable CIRQ<1> INT From XIO
Bit 44 Clr: Cmd/Data NOACK are Errors
Bit 56 Clr: IDLEBC Assert in Last Cycle 4
Bit 57 Clr: IDLEBC Assert During Cycle 4
Bit 59 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
Error Summary Reg (R1) x0000000000000000
EVB Control Register (R2) x0000006100000061
LOW LONGWORD Slice Follows
Bit 0 Set: Enable Addr-Cmd Parity Checking
Bit 5 Set: Enable Bcache ECC Corr QW0/QW2
Bit 6 Set: Enable ECC Check - QW0/QW2 Data
HIGH LONGWORD Slice Follows
Bit 32 Set: Enable Addr-Cmd Parity Check
Bit 37 Set: Enable Bcache ECC Corr QW1/QW3
Bit 38 Set: Enable ECC Check-QW1/QW3 Data
Victim Error Addr (R3) x02EC000602EC0006
LOW LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000002EC0006
HIGH LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000002EC0006
Correctable Err Reg (R4) x0000000000000000
LOW LONGWORD Slice Follows
QW0 ECC Syndrome: No Syndrome Bits Set
QW2 ECC Syndrome: No Syndrome Bits Set
HIGH LONGWORD Slice Follows
QW1 ECC Syndrome: No Syndrome Bits Set
QW3 ECC Syndrome: No Syndrome Bits Set
Correctable Err Addr (R5) xB800000AB800000A
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005800000A
Uncorrectable Error (R6) x8000000080000000
LOW LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW0 Uncorr ECC Syndrome x0000000000000000
QW2 Uncorr ECC Syndrome x0000000000000000
HIGH LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW1 Uncorr ECC Syndrome x0000000000000000
QW3 Uncorr ECC Syndrome x0000000000000000
Uncorrectable Err Adr(R7) xB800000EB800000E
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005800000E
EVB Reserve Register (R8) x0000000000000000
Duplicate Tag Control(R9) x0000011100000111
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Enable
Bit 4 Set: Enable Tag Ctrl Parity Checking
Bit 8 Set: Enable Tag Parity Checking
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Enable
Bit 36 Set: Enable Tag Ctl Parity Checking
Bit 40 Set: Enable Tag Parity Checking
Duplicate Tag Error (R10) x0000000000000160
LOW LONGWORD Slice Follows
Dup Tag Store Err Adr x000000000000000B
Dup Tag Test Control(R11) x0000000000000000
LOW LONGWORD Slice Follows
Bit 3 Clr: Write Good Control Store Parity
Bit 31 Clr: Write Good Tag Store Parity
Duplicate Tag Address x0000000000000000
MUX'ed Tag/Addr Field x0000000000000000
Partial Tag Field x0000000000000000
Duplicate Tag Test (R12) x5B00000D5B00000D
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Dirty Bit
Bit 2 Set: Duplicate Tag Valid Bit
Bit 3 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x00000000000005B0
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Dirty Bit
Bit 34 Set: Duplicate Tag Valid Bit
Bit 35 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x00000000000005B0
Dup Tag Reserve Reg (R13) x0000000000000000
I-Bus Control Stat (R14) x0000100000001000
LOW LONGWORD Slice Follows
Bit 12 Set: Enable I-Bus Parity Check
HIGH LONGWORD Slice Follows
Bit 44 Set: Enable I-Bus Parity Check
I-Bus Error Addr Reg(R15) x4F407043E040007B
LOW LONGWORD Slice Follows
C-Bus<31:0> C/A Data x00000000E040007B
HIGH LONGWORD Slice Follows
C-Bus<63:32> C/A Data x000000004F407043
Arbitration Ctrl Reg(R16) x0000012000000120
LOW LONGWORD Slice Follows
Bit 5 Set: C-Bus2 DONATE Mode Enabled
Bit 8 Set: C-Bus2 PAWN Mode Enabled
HIGH LONGWORD Slice Follows
Bit 37 Set: C-Bus2 DONATE Mode Enabled
Bit 40 Set: C-Bus2 PAWN Mode Enabled
C-Bus2 Control Reg (R17) x0000110100001001
LOW LONGWORD Slice Follows
Bit 0 Set: C-Bus2 Parity Checking Enabled
Bit 12 Set: Enable C-Bus2 Error Interrupt
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Parity Checking Enabled
CPU Cmdr ID Field: C-Bus2 CPU #0 ID
Bit 44 Set: Enable C-Bus2 Error Interrupt
C-Bus2 Error Reg (R18) x0000000000000000
C-Bus2 Err Addr Low (R19) x4F407043E040009B
LOW LONGWORD Slice Follows
CBus CAD<31:0> Er Adr x00000000E040009B
HIGH LONGWORD Slice Follows
CBus CAD<95:64> Er Adr x000000004F407043
C-Bus2 Err Addr High(R20) x0F407043E04000A3
LOW LONGWORD Slice Follows
CBus CAD<63:32> Er Adr x00000000E04000A3
HIGH LONGWORD Slice Follows
CBus CAD<127:96> Er Adr x000000000F407043
C-Bus2 Reserve Reg (R21) x0000000000000000
Address Lock Reg (R22) x006DDB41006DDB41
LOW LONGWORD Slice Follows
Bit 0 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000036EDA
HIGH LONGWORD Slice Follows
Bit 32 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000036EDA
Proc Mailbox Reg (R23) x0000000000000000
Inter-Proc Int Req (R24) x0000000000000000
System Int Clear Reg(R25) x0000000000000000
Perf Monitor Ctl Reg(R26) x0000000000000000
Perf Monitor Reg 1 (R27) x0000000000000000
Perf Monitor Reg 2 (R28) x0000000000000000
Perf Monitor Reg 3 (R29) x0000000000000000
Perf Monitor Reg 4 (R30) x0000000000000000
Perf Monitor Reg 5 (R31) x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE00008523040590
Bit 4 Set: PCI Slot 0 Present
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 10 Set: EV5 Exclusive Exchange Enabled 4
Bit 18 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 29 Set: CBUS Parity Checking Enabled
Bit 32 Set: CBUS Back-to-Back Cycles Enbld
T2 Revision: Pass 3
State Machine Vis Select: CBUS Cyc Counter
Bit 39 Set: PCI Slot 2 Present
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter Enabled
Bit 59 Set: PCI SERR# Interrupts Enabled
Bit 60 Set: PCI PERR# Interrupts Enabled
Bit 61 Set: PCI Rd Data Prty Inter Enabled
Bit 62 Set: PCI Adr Parity Inter Enabled
Bit 63 Set: PCI Wrt Data Prty Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000040000
Bit 18 Set: Invalid PFN Error
CERR2 Failed C/A <63:00> x002C0000002C0000
CERR3 Failed C/A <127:64> xF083FFFFF083FFFF
PERR1 PCI Error Reg 1 x0000000000000000
PERR2 PCI Cmd & Err Addr x0000000600000000
Failed Cmd & Addr Valid When Parity Error
Failed PCI Cmd: x6 Memory Read
PCI Error Address: x0000000000000000
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD <31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x000000000010603F
PC Hole End Addr: x000000000000003F
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x0000000000000000
PCI Window End Adr: x0000000000000000
PCI Window Start Adr: x0000000000000000
WMASK1 Window Mask Reg 1 x0000000000000000
PCI Window Mask: x0000000000000000
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr: x0000000000000000
WBASE2 Window Base Reg 2 x00000000000C03FF
PCI Window End Adr: x00000000000003FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr:x0000000000000000
WMASK2 Window Mask Reg 2 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE2 Translated Base R2 x0000000000580000
Translated Base Addr: x0000000000002C00
TDR0 TLB Data Register 0 x0000000000000000
TDR0 Data is Invalid
TLB Entry 0 Tag Data x0000000000000000
TLB Entry 0 PFN Data x0000000000000000
TDR1 TLB Data Register 1 x0000002400000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data x0000000000000000
TLB Entry 1 PFN Data x0000000000000012
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data x0000000000000000
TLB Entry 2 PFN Data x0000000000000000
TDR3 TLB Data Register 3 x0000000000000003
TDR3 Data is Invalid
TLB Entry 3 Tag Data x0000000000000003
TLB Entry 3 PFN Data x0000000000000000
TDR4 TLB Data Register 4 x0000000000000000
TDR4 Data is Invalid
TLB Entry 4 Tag Data x0000000000000000
TLB Entry 4 PFN Data x0000000000000000
TDR5 TLB Data Register 5 x0000000000000000
TDR5 Data is Invalid
TLB Entry 5 Tag Data x0000000000000000
TLB Entry 5 PFN Data x0000000000000000
TDR6 TLB Data Register 6 x0000000000000000
TDR6 Data is Invalid
TLB Entry 6 Tag Data x0000000000000000
TLB Entry 6 PFN Data x0000000000000000
TDR7 TLB Data Register 7 x0000000000000000
TDR7 Data is Invalid
TLB Entry 7 Tag Data x0000000000000000
TLB Entry 7 PFN Data x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x0000000000000000
Command Trap Register 1 xE2000008E2000008
Command Trap Register 2 x0020742F4020742F
Configuration Register x8009506880095068
EDC Status Register 1 x003D000A0A49000A
[Even] Read CBITS <11:0> x000000000000000A
[Even] Write CBITS <11:0>x0000000000000A49
[Odd] Read CBITS <11:0> x000000000000000A
[Odd] Write CBITS <11:0> x000000000000003D
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
Error Register 1 x0000000000000000
Command Trap Register 1 xE2400008E2400008
Command Trap Register 2 x0020742F4020742F
Configuration Register x8019506980195069
EDC Status Register 1 x000A0540000A07F8
[Even] Read CBITS <11:0> x00000000000007F8
[Even] Write CBITS <11:0>x000000000000000A
[Odd] Read CBITS <11:0> x0000000000000540
[Odd] Write CBITS <11:0> x000000000000000A
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
Error Register 1 x0000000000000000
Command Trap Register 1 xE2800008E2800008
Command Trap Register 2 x00206DAF40206DAF
Configuration Register x8029506A8029506A
EDC Status Register 1 x0436042D01CA042D
[Even] Read CBITS <11:0> x000000000000042D
[Even] Write CBITS <11:0>x00000000000001CA
[Odd] Read CBITS <11:0> x000000000000042D
[Odd] Write CBITS <11:0> x0000000000000436
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000003
Error Register 1 x0000000000000000
Command Trap Register 1 xE2C00008E2C00008
Command Trap Register 2 x00206DAF40206DAF
Configuration Register x8039506B8039506B
EDC Status Register 1 x0CFF03AF0E0C04BE
[Even] Read CBITS <11:0> x00000000000004BE
[Even] Write CBITS <11:0>x0000000000000E0C
[Odd] Read CBITS <11:0> x00000000000003AF
[Odd] Write CBITS <11:0> x0000000000000CFF
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0> x000000000000000D
[Odd] Syndrome <11:0> x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITS x0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Selectx0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Selectx0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
******************************** ENTRY 4********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 1.
Timestamp of occurrence 28-MAY-1997 10:57:15
Host name hx23
System type register x00000009 AlphaServer 2x00
Number of CPUs (mpnum) x00000002
CPU logging event (mperr) x00000001
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
-- ENTRY FRAME FOLLOWS --
Frame ID x00000022 Machine Check Frame
CPU Number Logging Event 1.
- ALPHA EV5 COMMON REGS -
Flags: x00000001
Machine Check Error Code x00000202 CPU Detected Unrecoverable Error
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x0000000000000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 xFFFFFFFFB6918000
PALTEMP1 x0000000000000001
PALTEMP2 xFFFFFC00004DCFA0
PALTEMP3 x0000000000004800
PALTEMP4 x0000000000000002
PALTEMP5 x0000000000000000
PALTEMP6 x0000000027B5FA1D
PALTEMP7 xFFFFFC00004DCA20
PALTEMP8 x1F1E161514020100
PALTEMP9 xFFFFFC00004DCD10
PALTEMP10 xFFFFFC00003986DC
PALTEMP11 xFFFFFC00004DCB70
PALTEMP12 xFFFFFC00004DCF10
PALTEMP13 x0000012000000120
PALTEMP14 x0000000000000001
PALTEMP15 x0000000000000000
PALTEMP16 x0000020306600109
PALTEMP17 x0000000000000000
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFFB691B978
PALTEMP20 x0000000000A00000
PALTEMP21 xFFFFFC00004DCF40
PALTEMP22 xFFFFFC0000671320
PALTEMP23 x000000007397FA58
Exception Address Reg xFFFFFC00003986DC
Native-mode Instruction
Exception PC x3FFFFF00000E61B7
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode:x0000000000000005
Interrupt Summary Reg x0000000000000000
AST Requests 3-0:x0000000000000000
IBOX Ctrl and Status Reg x0000004160800000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFFB68FBD38
Memory Mgmt Flt Sts Reg x00000000000166D1
If Error, Reference Which Caused Was Write
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field: x000000000000001B
Fault Inst Opcode: x000000000000002C
Scache Address Reg xFFFFFF00000190FF
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFF80704EEFFF
Last Bcache Access Resulted in a Miss.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is Set.
Value of Tag Control Shared Bit is Set.
Value of Tag Control Valid Bit is Clear.
Value of Parity Bit Covering Tag Store
Address Bits is Set.
Tag Address<38:20> Is: x0000000000000704
Ext Interface Address Reg xFFFFFF000000000F
Fill Syndrome Reg x00000000000041FA
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF000020020F
- SYSTEM SPECIFIC REGS -
Configuration Reg (R0) x380000F238000002
LOW LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 12 Clr: Cmd/Data NOACK are Errors
Bit 24 Clr: IDLEBC Assert in Last Cycle 4
Bit 25 Clr: IDLEBC Assert During Cycle 4
Bit 27 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
HIGH LONGWORD Slice Follows
RATTLER Gate Array: Revision #2
Bit 36 Set: Rx IPL31 on CBus CERR Assert
Bit 37 Set: Rx HALT on CBus SYS_EVENT
Bit 38 Set: Rx HALT on IIRR CSR24 HALT Req
Bit 39 Set: Rx INTERPROC INT on Write to
IIRR CSR24 INTERPROC INT Req
Bit 44 Clr: Cmd/Data NOACK are Errors
Bit 56 Clr: IDLEBC Assert in Last Cycle 4
Bit 57 Clr: IDLEBC Assert During Cycle 4
Bit 59 Set: ACK Set_Dirty & Set_Lock Cmds
CACHE Size Field: 4 MB Cache
Error Summary Reg (R1) x0000000000000000
EVB Control Register (R2) x0000006100000061
LOW LONGWORD Slice Follows
Bit 0 Set: Enable Addr-Cmd Parity Checking
Bit 5 Set: Enable Bcache ECC Corr QW0/QW2
Bit 6 Set: Enable ECC Check - QW0/QW2 Data
HIGH LONGWORD Slice Follows
Bit 32 Set: Enable Addr-Cmd Parity Check
Bit 37 Set: Enable Bcache ECC Corr QW1/QW3
Bit 38 Set: Enable ECC Check-QW1/QW3 Data
Victim Error Addr (R3) x0704000607040006
LOW LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000007040006
HIGH LONGWORD Slice Follows
EVB<33:4> Victim Addr x0000000007040006
Correctable Err Reg (R4) x0000000000000000
LOW LONGWORD Slice Follows
QW0 ECC Syndrome: No Syndrome Bits Set
QW2 ECC Syndrome: No Syndrome Bits Set
HIGH LONGWORD Slice Follows
QW1 ECC Syndrome: No Syndrome Bits Set
QW3 ECC Syndrome: No Syndrome Bits Set
Correctable Err Addr (R5) xB810000A00000662
LOW LONGWORD Slice Follows
Bit 32 Clr: EV-Bus Bit 39, IO Bit,Clr
EVB<34:4> Corr Err Adr x0000000000000662
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Corr Err Adr x000000005810000A
Uncorrectable Error (R6) x8000000080000000
LOW LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW0 Uncorr ECC Syndrome x0000000000000000
QW2 Uncorr ECC Syndrome x0000000000000000
HIGH LONGWORD Slice Follows
EVB<3:0> CMD: Command Field = x8
QW1 Uncorr ECC Syndrome x0000000000000000
QW3 Uncorr ECC Syndrome x0000000000000000
Uncorrectable Err Adr(R7) xB810000EB810000E
LOW LONGWORD Slice Follows
Bit 32 Set: EV-Bus Bit 39, IO Bit, Set
EVB<34:4> Uncor Err Adr x000000005810000E
HIGH LONGWORD Slice Follows
Bit 63 Set: EV-Bus Bit 39, IO Bit,Set 4
EVB<34:4> Uncor Err Adr x000000005810000E
EVB Reserve Register (R8) x0000000000000000
Duplicate Tag Control(R9) x0000011100000111
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Enable
Bit 4 Set: Enable Tag Ctrl Parity Checking
Bit 8 Set: Enable Tag Parity Checking
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Enable
Bit 36 Set: Enable Tag Ctl Parity Checking
Bit 40 Set: Enable Tag Parity Checking
Duplicate Tag Error (R10) x0000000000000100
LOW LONGWORD Slice Follows
Dup Tag Store Err Adr x0000000000000008
Dup Tag Test Control(R11) x0000000000000000
LOW LONGWORD Slice Follows
Bit 3 Clr: Write Good Control Store Parity
Bit 31 Clr: Write Good Tag Store Parity
Duplicate Tag Address x0000000000000000
MUX'ed Tag/Addr Field x0000000000000000
Partial Tag Field x0000000000000000
Duplicate Tag Test (R12) x4A00000D4A00000D
LOW LONGWORD Slice Follows
Bit 0 Set: Duplicate Tag Dirty Bit
Bit 2 Set: Duplicate Tag Valid Bit
Bit 3 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x00000000000004A0
HIGH LONGWORD Slice Follows
Bit 32 Set: Duplicate Tag Dirty Bit
Bit 34 Set: Duplicate Tag Valid Bit
Bit 35 Set: TAG Control Parity Bit
Dup Tag RAM, TAG Data x00000000000004A0
Dup Tag Reserve Reg (R13) x0000000000000000
I-Bus Control Stat (R14) x0000100000001000
LOW LONGWORD Slice Follows
Bit 12 Set: Enable I-Bus Parity Check
HIGH LONGWORD Slice Follows
Bit 44 Set: Enable I-Bus Parity Check
I-Bus Error Addr Reg(R15) x4F207443E0000073
LOW LONGWORD Slice Follows
C-Bus<31:0> C/A Data x00000000E0000073
HIGH LONGWORD Slice Follows
C-Bus<63:32> C/A Data x000000004F207443
Arbitration Ctrl Reg(R16) x0000012000000120
LOW LONGWORD Slice Follows
Bit 5 Set: C-Bus2 DONATE Mode Enabled
Bit 8 Set: C-Bus2 PAWN Mode Enabled
HIGH LONGWORD Slice Follows
Bit 37 Set: C-Bus2 DONATE Mode Enabled
Bit 40 Set: C-Bus2 PAWN Mode Enabled
C-Bus2 Control Reg (R17) x0000120100001201
LOW LONGWORD Slice Follows
Bit 0 Set: C-Bus2 Parity Checking Enabled
Bit 12 Set: Enable C-Bus2 Error Interrupt
HIGH LONGWORD Slice Follows
Bit 32 Set: C-Bus2 Parity Checking Enabled
CPU Cmdr ID Field: C-Bus2 CPU #1 ID
Bit 44 Set: Enable C-Bus2 Error Interrupt
C-Bus2 Error Reg (R18) x0000000000000000
C-Bus2 Err Addr Low (R19) x4F207443E0000093
LOW LONGWORD Slice Follows
CBus CAD<31:0> Er Adr x00000000E0000093
HIGH LONGWORD Slice Follows
CBus CAD<95:64> Er Adr x000000004F207443
C-Bus2 Err Addr High(R20) x0F207443E000009B
LOW LONGWORD Slice Follows
CBus CAD<63:32> Er Adr x00000000E000009B
HIGH LONGWORD Slice Follows
CBus CAD<127:96> Er Adr x000000000F207443
C-Bus2 Reserve Reg (R21) x0000000000000000
Address Lock Reg (R22) x0020020100200201
LOW LONGWORD Slice Follows
Bit 0 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000010010
HIGH LONGWORD Slice Follows
Bit 32 Set: Lock Address Field Valid
EV<30:5> Lock Address x0000000000010010
Proc Mailbox Reg (R23) x0000000000000000
Inter-Proc Int Req (R24) x0000000000000000
System Int Clear Reg(R25) x0000000000000000
Perf Monitor Ctl Reg(R26) x0000000000000000
Perf Monitor Reg 1 (R27) x0000000000000000
Perf Monitor Reg 2 (R28) x0000000000000000
Perf Monitor Reg 3 (R29) x0000000000000000
Perf Monitor Reg 4 (R30) x0000000000000000
Perf Monitor Reg 5 (R31) x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000011 T2 System-Bus to PCI Bridge Frame
IO Control/Status Reg xFE00008523040590
Bit 4 Set: PCI Slot 0 Present
Bit 7 Set: TLB Error Checking Enabled
Bit 8 Set: CBUS CXACK Check Enabled
Bit 10 Set: EV5 Exclusive Exchange Enabled
Bit 18 Set: PCI Slot 1 Present
Bit 24 Set: NOACK, CUCERR, OutOfSync Enbld
Bit 25 Set: PCI Memory Space Enabled
Bit 29 Set: CBUS Parity Checking Enabled
Bit 32 Set: CBUS Back-to-Back Cycles Enbld
T2 Revision: Pass 3
State Machine Vis Select: CBUS Cyc Counter
Bit 39 Set: PCI Slot 2 Present
Bit 57 Set: PCI NMI Interrupts Enabled
Bit 58 Set: PCI Dev Timeout Inter Enabled
Bit 59 Set: PCI SERR# Interrupts Enabled
Bit 60 Set: PCI PERR# Interrupts Enabled
Bit 61 Set: PCI Rd Data Prty Inter Enabled
Bit 62 Set: PCI Adr Parity Inter Enabled
Bit 63 Set: PCI Wrt Data Prty Inter Enbled
CERR1 CBUS Error Reg 1 x0000000000040000
Bit 18 Set: Invalid PFN Error
CERR2 Failed C/A <63:00> x002C0000002C0000
CERR3 Failed C/A <127:64> xF083FFFFF083FFFF
PERR1 PCI Error Reg 1 x0000000000000000
PERR2 PCI Cmd & Err Addr x0000000600000000
Failed Cmd & Addr Valid When Parity Error
Failed PCI Cmd: x6 Memory Read
PCI Error Address: x0000000000000000
HAE0_1 High Adr Ext Reg 1 x0000000000000010
HAE0_1 <4:0> is Sparse Mem PCI_AD <31:27>
HAE0_2 High Adr Ext Reg 2 x0000000000000000
HBASE PC Hole Base Reg x000000000010603F
PC Hole End Addr: x000000000000003F
Bit 13 Set: PC Hole Enable 1
Bit 14 Set: PC Hole Enable 2
PC Hole Start Addr: x0000000000000020
WBASE1 Window Base Reg 1 x0000000000000000
PCI Window End Adr: x0000000000000000
PCI Window Start Adr:x0000000000000000
WMASK1 Window Mask Reg 1 x0000000000000000
PCI Window Mask: x0000000000000000
TBASE1 Translated Base R1 x0000000000000000
Translated Base Addr: x0000000000000000
WBASE2 Window Base Reg 2 x00000000000C03FF
PCI Window End Adr: x00000000000003FF
Bit 18 Set: Scatter-Gather Enable
Bit 19 Set: PCI Window Enable
PCI Window Start Adr: x0000000000000000
WMASK2 Window Mask Reg 2 x000000003FF00000
PCI Window Mask: x00000000000003FF
TBASE2 Translated Base R2 x0000000000580000
Translated Base Addr: x0000000000002C00
TDR0 TLB Data Register 0 x0000000000000000
TDR0 Data is Invalid
TLB Entry 0 Tag Data x0000000000000000
TLB Entry 0 PFN Data x0000000000000000
TDR1 TLB Data Register 1 x0000002400000000
TDR1 Data is Invalid
TLB Entry 1 Tag Data x0000000000000000
TLB Entry 1 PFN Data x0000000000000012
TDR2 TLB Data Register 2 x0000000000000000
TDR2 Data is Invalid
TLB Entry 2 Tag Data x0000000000000000
TLB Entry 2 PFN Data x0000000000000000
TDR3 TLB Data Register 3 x0000000000000003
TDR3 Data is Invalid
TLB Entry 3 Tag Data x0000000000000003
TLB Entry 3 PFN Data x0000000000000000
TDR4 TLB Data Register 4 x0000000000000000
TDR4 Data is Invalid
TLB Entry 4 Tag Data x0000000000000000
TLB Entry 4 PFN Data x0000000000000000
TDR5 TLB Data Register 5 x0000000000000000
TDR5 Data is Invalid
TLB Entry 5 Tag Data x0000000000000000
TLB Entry 5 PFN Data x0000000000000000
TDR6 TLB Data Register 6 x0000000000000000
TDR6 Data is Invalid
TLB Entry 6 Tag Data x0000000000000000
TLB Entry 6 PFN Data x0000000000000000
TDR7 TLB Data Register 7 x0000000000000000
TDR7 Data is Invalid
TLB Entry 7 Tag Data x0000000000000000
TLB Entry 7 PFN Data x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000000
Error Register 1 x0000000000000000
Command Trap Register 1 xE2000008E2000008
Command Trap Register 2 x004073D3404073D3
Configuration Register x8009506880095068
EDC Status Register 1 x003D000A0A49000A
[Even] Read CBITS <11:0> x000000000000000A
[Even] Write CBITS <11:0>x0000000000000A49
[Odd] Read CBITS <11:0>x000000000000000A
[Odd] Write CBITS <11:0> x000000000000003D
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0>x000000000000000D
[Odd] Syndrome <11:0>x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITSx0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Select x0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Selectx0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000001
Error Register 1 x0000000000000000
Command Trap Register 1 xE2400008E2400008
Command Trap Register 2 x004073D3404073D3
Configuration Register x8019506980195069
EDC Status Register 1 x000A0540000A07F8
[Even] Read CBITS <11:0>x00000000000007F8
[Even] Write CBITS <11:0>x000000000000000A
[Odd] Read CBITS <11:0>x0000000000000540
[Odd] Write CBITS <11:0>x000000000000000A
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0>x000000000000000D
[Odd] Syndrome <11:0>x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITSx0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Selectx0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Select x0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000002
Error Register 1 x0000000000000000
Command Trap Register 1 xE2800008E2800008
Command Trap Register 2 x004073D3404073D3
Configuration Register x8029506A8029506A
EDC Status Register 1 x0436042D01CA042D
[Even] Read CBITS <11:0>x000000000000042D
[Even] Write CBITS <11:0>x00000000000001CA
[Odd] Read CBITS <11:0>x000000000000042D
[Odd] Write CBITS <11:0>x0000000000000436
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0>x000000000000000D
[Odd] Syndrome <11:0>x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITSx0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Selectx0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Selectx0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000008 Memory Frame
Memory Module ID x00000003
Error Register 1 x0000000000000000
Command Trap Register 1 xE2C00008E2C00008
Command Trap Register 2 x004073D3404073D3
Configuration Register x8039506B8039506B
EDC Status Register 1 x0CFF03AF0E0C04BE
[Even] Read CBITS <11:0>x00000000000004BE
[Even] Write CBITS <11:0>x0000000000000E0C
[Odd] Read CBITS <11:0>x00000000000003AF
[Odd] Write CBITS <11:0>x0000000000000CFF
EDC Status Register 2 x000000170000000D
[Even] Syndrome <11:0>x000000000000000D
[Odd] Syndrome <11:0>x0000000000000017
EDC Control Register x2000000020000000
[Even] Substitute Read Cbits Used
[Even] Substitute Write Cbits Used
[Even] Disable Inbound Parity Check
[Even] Enable EDC swap Mode
[Even] Complement Read Data Parity
[Even] Disable EDC Correction
[Even] Disable EDC Reporting
[Odd] Substitute Read Cbits Used
[Odd] Substitute Write Cbits Used
[Odd] Disable Inbound Parity Check
[Odd] Enable EDC swap Mode
[Odd] Complement Read Data Parity
[Odd] Disable EDC Correction
[Odd] Disable EDC Reporting
[Even] Subs. Read CBITS <x0000000000000000
[Even] Subs. Write CBITSx0000000000000000
[Odd] Subs. Read CBITS <1x0000000000000000
[Odd] Subs. Write CBITS <x0000000000000000
Stream Buffer Control Reg x0000080000000800
Refresh Control Register x000001D8000001D8
[Even] Refresh Enable
[Odd] Refresh Enable
[Even] Syndrome Mask <11:x00000000000000D8
[Odd] Syndrome Mask <11:0x00000000000000D8
Filter Control Register x0000000000000000
[Even] Syndrome Mask <11:x0000000000000000
[Even] Bank Selectx0000000000000000
[Odd] Syndrome Mask <11:0x0000000000000000
[Odd] Bank Selectx0000000000000000
-- ENTRY FRAME FOLLOWS --
Frame ID x00000000 End Frame
hx23>
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