| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 922.1 | Some answers | WIBBIN::NOYCE | Otherwise, pound the table | Wed Oct 21 1992 09:40 | 51 |
| 922.2 | | UNTADH::BRETT | Fate just keeps on happening | Mon Nov 02 1992 16:20 | 4 |
| 922.3 | Instruction latencies... | CVG::PETTENGILL | mulp | Mon Nov 02 1992 16:27 | 4 |
| 922.4 | branch latencies? | RGB::SEILER | Larry Seiler | Wed Nov 04 1992 17:48 | 27 |
| 922.5 | I may be wrong on the mispredicted ones | KAMPUS::NEIDECKER | Software Motion Pictures | Thu Nov 05 1992 03:58 | 29 |
| 922.6 | | RGB::SEILER | Larry Seiler | Thu Nov 05 1992 15:25 | 22 |
| 922.7 | | SMOP::GLOSSOP | Kent Glossop | Thu Nov 05 1992 15:46 | 4 |
| 922.8 | Would be nice, but | WIBBIN::NOYCE | Otherwise, pound the table | Thu Nov 05 1992 15:59 | 3 |
| 922.9 | Oops. Wrong processor | SMOP::GLOSSOP | Kent Glossop | Thu Nov 05 1992 16:12 | 1 |
| 922.10 | 21064 branching | LEGUP::SHORTT | John Shortt / 266-4594 | Tue Nov 10 1992 10:44 | 14 |
| 922.11 | How many cycles per instruction? | TAV02::GLASS | Yossi Glass (Hapoel 83, Macabbi 75) | Wed Jun 23 1993 05:41 | 14 |
| 922.12 | Could you rephrase your question? | WIBBIN::NOYCE | It's the memory interface, stupid! | Wed Jun 23 1993 09:34 | 9 |
| 922.13 | MIssing Latencies from Figure 2-5 | HDLITE::NEWMAN | Chuck Newman, 297-5499, MRO4-1/H16, Pole J13 | Wed Jun 23 1993 11:02 | 11 |
| 922.14 | Right, memory-system timing isn't well described | WIBBIN::NOYCE | It's the memory interface, stupid! | Wed Jun 23 1993 14:02 | 29 |
| 922.15 | reason for STx-LDx latency | LEGUP::SHORTT | John Shortt / 264-1695 | Wed Jun 23 1993 14:19 | 20 |
| 922.16 | | HDLITE::NEWMAN | Chuck Newman, 297-5499, MRO4-1/H16, Pole J13 | Wed Jun 23 1993 17:16 | 13
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