Conference wonder::turbolaser

> A customer made a statement about the bandwidth on the 8400 backplane
> that I really dont know how to answer.  His statement was:
> 
> "... (8) (EV56) 622Mhz CPU's and 6Gb of memory will flood the backplane 
>  thereby making the 8 CPU's less than fully useful."

Why don't you ask the customer to elaborate. He may not know what he's talking
about and may be simply regurgitating something he's been fed by a competitor.
Every Alpha product we've ever made has been memorybandwidth starved on some
applications - and in all likelihood - every future Alpha product will suffer
the same.

Bold statements like this, not based on a particular application profile,
are simply nonsense.

I am sure that it is the competition giving them this information.  I am in the process of getting
more information, but what you have in the note is the only information I have so far.  I am guessing
that the application is a database (OLTP).  Could you please let me know what other questions I
should be asking.  Thanks

-bill anderson

    Memory bandwidth is sometimes an extremely serious issue for Alpha. 
    But the reason for this is actually due to a major STRENGTH of Alpha:
    the chip is so bloody fast that it's hard to build memory systems that
    can feed it fast enough.
    
    This does NOT mean that Alpha's speed is wasted.  It means that
    applications with decent cache hit rates can take advantage of that
    speed, and applications with poor cache behaviour cannot.
    
    All other RISC vendors face the same problems; we just have the problem
    a bit more than they do because we have more speed in the chip itself.  
    
    For an introduction to memory bandwidth issues (which can be shared
    with customers if you deem it appropriate), see the competitive section
    of my homepage.  There's also a DIGITAL INTERNAL USE ONLY set of
    questions and answers, which you should definitely not share, but which
    may help you prepare for the customer's questions.
    
    /John Henning
     CSD Performance Group
     Digital Equipment Corporation
     [email protected]
     Speaking for myself, not Digital

     Digital Internal homepage: http://tlg-www.zko.dec.com/~henning
    

    
    .2 reposted for 80 columns
    
  <<< Note 1195.2 by NQOS01::16.90.80.201::nwd002.cxo.dec.com::anderson_bi >>>

    I am sure that it is the competition giving them this information.  I
    am in the process of getting more information, but what you have in the
    note is the only information I have so far.  I am guessing that the
    application is a database (OLTP).  Could you please let me know what
    other questions I should be asking.  Thanks

    -bill anderson

    

    The best use of the memory bandwidth of a turbo laser is made in case
    you have 4- or 8-way interleaving.
    6 GB of memory will be set to 2-way interleaving only.
    Peter.

	I encourage you to ask more questions about what the appliaction is
	really all about.

	In the meantime, check out the TPC (C&D) numbers we have already
	posted for eight cpu configurations. You should also contact John
	Henning directly. He may have data he can share with you (in a
	retricted way) that is not yet publically available.

 >The best use of the memory bandwidth of a turbo laser is made in case
 >you have 4- or 8-way interleaving.
 >6 GB of memory will be set to 2-way interleaving only.
 >Peter.

Could you explain interleaving in a little more detail?  I have a general
idea what it is, but how is it that 6GB is only 2-way interleaving?
How do I get to 4 or 8 way interleaving?  Are these specific memory
options in 8x00 to get this.  Thanks.

-bill

    use the commands documented in
    
    http://labrea.zko.dec.com/~henning/Mem_bw.html

The web page referenced in .8, 
http://labrea.zko.dec.com/~henning/Mem_bw.html,
says 
"If you have 2GB of memory in your system configured as 4 boards of 512MB 
apiece, you will get about 1 GB/second bandwidth on the Streams 
benchmark. If you have 2GB of memory configured as a single 2GB board, 
you will get about 1/2 GB/sec."

Where you say "configured as 4 boards of 512MB apiece" do you mean four 
*banks*, i.e. two 1GB boards?

This would make more sense to me, because it allow a higher degree of 
interleaving, four banks of 512 each.

Thanks,

Bruce
Sales Support, MCI Account Team

    
    
    64mb = 1 bank
    128mb, 256mb, 512mb, 1gb, and 2gb boards are all 2 banks.
    4gb boards are either 2 banks or 4 banks depending on the number of
    memory boards/banks in the configuration.
    
    So 4 512mb boards would give you 8 banks, where a single 2gb board
    would only be 2 banks.
    
    

re: .10   
 >>So 4 512mb boards would give you 8 banks, where a single 2gb      
 >>board would only be 2 banks.
    
I respectfully disagree.  There's no way to get a (customer 
orderable) "full" 512MB memory board, i.e. two banks, for an 8x00.  
The MS7CC-DA is 512MB, albeit on a 1GB memory board with one bank 
populated.  The MS7CC-UB is 512MB of memory to populate the other 
half of the -DA, giving 1GB in/on two banks.

Two MS7CC-DAs plus two MS7CC-UB will give *four banks of 512MB 
apiece,* which is what I was suggesting John Henning meant to say on 
the referenced web page.

Bruce
only_trying_to_clarify_boards_vs_banks_for_purposes_of_interleaving

    Hmmm.   Let me try 1195.9 again.
    
    I believe that the sweet spot for turbolaser is 8x8, meaning 8 cpus and
    8 banks, meaning 4 cpu cards and 4 memory cards - for most memory
    options.
    
    .10 clarifies that if you somehow found a 64mb board somewhere (we
    really make a TL option that small?) it would give you only 1 bank
    per card.  And if you have 4gb board it already comes with 4 banks
    on one card.
    
    Meanwhile, .11 points out that it is possible to buy half-populated
    boards and then fully populate them, and concludes that 4
    half-populated boards must have 4 banks.  But I suspect that conclusion
    may be unwarranted, since the author of .10 appears to work in the
    Turbolaser engineering group.
    
    .11, what is your basis for believing that only "full" memory boards
    have 2 banks?  Perhaps a configuration or ordering guide somewhere
    needs to be clarified.   Please quote chapter and verse.
    
    thanks
        /john
    

    
     Please make sure you have your facts straight. It is not in our best
    intrest (Digital) to possibly tell a customer/other noters statements
    that are simply false. This notes file has numerous references to
    Turbo memory configs that discuss banks and interleaving. 
    
     See notes 315, 666, 982. 
    
    In a nutshell. We NEVER produced a single-bank TurboLAser memory
    module for production. The 128,256,512,1024 and 2048 Mbytes modules
    are 2-bank modules. The 4096 (4 gig) is a 4-bank/2-bank module.
    Interleaving will always configure the maximum interleave it can.
    3 512's for example will be config'd as a 4-way + a 2-way
    
    
    
    						/Dave
     

             <<< WONDER::SOFT1$:[NOTES$LIBRARY]TURBOLASER.NOTE;1 >>>
         -< TurboLaser Notesfile - AlphaServer 8200 and 8400 systems >-
================================================================================
Note 1195.13                 8400 Bandwidth again...                    13 of 13
DANGER::HARTWELL                                     18 lines  20-MAY-1997 14:11
--------------------------------------------------------------------------------

	RE .11
    
     Please make sure you have your facts straight. It is not in our best
    intrest (Digital) to possibly tell a customer/other noters statements
    that are simply false. This notes file has numerous references to
    Turbo memory configs that discuss banks and interleaving. 
    
     See notes 315, 666, 982. 
    
    In a nutshell. We NEVER produced a single-bank TurboLAser memory
    module for production. The 128,256,512,1024 and 2048 Mbytes modules
    are 2-bank modules. The 4096 (4 gig) is a 4-bank/2-bank module.
    Interleaving will always configure the maximum interleave it can.
    3 512's for example will be config'd as a 4-way + a 2-way
    
    
    
    						/Dave
     

I have set my notes .9 and .11 hidden, because, I am convinced :-) 
that they contain false and misleadig information.  I have read notes
315, 666 and 982.  Such reading and the gentle nudging of notes .12 
an .13 have convinced me that I don't know as much about configuring 
for interleaving as I thought.

I thought I had learned that all TurboLaser memory modules (i.e., the 
thing that plugs into the backplane/centerplane) have two banks, one 
of which might be empty, for example in the cases of MS7CC-BA and 
-DA.  

I further thought that the degree of memory interleaving was a linear 
function of the number of CPUs matched to the number of populated 
memory banks. That is, two CPUs and a single, fully populated memory 
module provides two-way interleaving.  

How is this incorrect?  Perhaps even a half-populated memory module 
has two-way interleaving and a fully populated memory module still 
has only two-way but with twice the memory (except for 4GB modules, 
of course, which support two- or four-way interleaving)?

Please help me understand and forgive me if I seem extra dense.

Thanks,

Bruce

I thought I had learned that all TurboLaser memory modules (i.e., the 
thing that plugs into the backplane/centerplane) have two banks, one 
of which might be empty, for example in the cases of MS7CC-BA and 
-DA.  

>>> 128,256,512,1gig,2gig all have 2 banks and by default each one is
>>> 2-way interleaved by itself. The 4gig has 4 banks and can be 2-way
>>> or 4-way interleaved.


I further thought that the degree of memory interleaving was a linear 
function of the number of CPUs matched to the number of populated 
memory banks. That is, two CPUs and a single, fully populated memory 
module provides two-way interleaving.  

>>> It has nothing to do with the number of CPU's. It totally depends
>>> upon the number of memory modules and the size of each memory module.
>>> Console will attempt to optimize the max possible interleave based upon
>>> the memory modules installed. 

How is this incorrect?  Perhaps even a half-populated memory module 
has two-way interleaving and a fully populated memory module still 
has only two-way but with twice the memory (except for 4GB modules, 
of course, which support two- or four-way interleaving)?

>>> Yes, the above is true.