Conference wonder::turbolaser

1162.0. "CPU 0 has CPU_TST Disabled in the NVR" by KERNEL::ROBB () Fri Apr 04 1997 11:22

    Does anyone know what this message means?
    
    CPU 0 has CPU_TST Disabled in the NVR
    
It does not appear on all systems on the site, only those with the firmware
upgraded.

    Here is an example of where it appears at init time.
27-MAR-1997 09:28:16.07 RLIV05 Initializing...
27-MAR-1997 09:28:35.99 RLIV05
27-MAR-1997 09:28:36.07 RLIV05 F   E   D   C   B   A   9   8   7   6   5   4   3
   2   1   0   NODE #
27-MAR-1997 09:28:36.15 RLIV05                             A   A   M   M   .   .
   .   P   P   TYP
27-MAR-1997 09:28:36.17 RLIV05                             o   o   +   +   .   .
   .  ++  ++   ST1
27-MAR-1997 09:28:36.29 RLIV05                             .   .   .   .   .   .
   .  EE  EB   BPD
27-MAR-1997 09:28:39.51 RLIV05                             o   o   +   +   .   .
   .  ++  ++   ST2
27-MAR-1997 09:28:39.67 RLIV05                             .   .   .   .   .   .
   .  EE  EB   BPD
27-MAR-1997 09:28:41.22 RLIV05                             +   +   +   +   .   .
   .  ++  ++   ST3
27-MAR-1997 09:28:41.40 RLIV05                             .   .   .   .   .   .
   .  EE  EB   BPD
27-MAR-1997 09:29:47.03 RLIV05
27-MAR-1997 09:29:47.11 RLIV05                                 .   +   +   +   .
   +   +   +   C0 PCI +
27-MAR-1997 09:29:47.17 RLIV05                 +   .   .   .   .   +   .   .   .
   .   .   .   C1 PCI +
27-MAR-1997 09:29:47.20 RLIV05
27-MAR-1997 09:29:47.27 RLIV05                 +   .   .   .   .   +   .   .   .
   .   .   .   C4 PCI +
27-MAR-1997 09:29:47.35 RLIV05 .   .   .   .   .   .   .   .   .   .   .   .   .
   .   .   .   C5
27-MAR-1997 09:29:47.43 RLIV05 .   .   .   .   .   .   .   .   .   .   .   .   .
   .   .   .   C6
27-MAR-1997 09:29:47.51 RLIV05 .   .   .   .   .   .   .   .   .   .   .   .   .
   .   .   .   C7
27-MAR-1997 09:29:47.51 RLIV05
27-MAR-1997 09:29:47.59 RLIV05                             .   .  A1  A0   .   .
   .   .   .   ILV
27-MAR-1997 09:29:47.66 RLIV05                             .   . 2GB 2GB   .   .
   .   .   .   4GB
27-MAR-1997 09:29:47.83 RLIV05 AlphaServer 8400 Console V4.8-6, 12-FEB-1997 16:3
1:47, SROM V3.1
27-MAR-1997 09:29:47.91 RLIV05 Configuring I/O adapters...
27-MAR-1997 09:29:47.99 RLIV05 isp0, slot 0, bus 0, hose0
27-MAR-1997 09:29:48.30 RLIV05 isp1, slot 1, bus 0, hose0
27-MAR-1997 09:29:48.70 RLIV05 tulip0, slot 2, bus 0, hose0
27-MAR-1997 09:29:52.55 RLIV05 isp2, slot 4, bus 0, hose0
27-MAR-1997 09:29:52.87 RLIV05 isp3, slot 5, bus 0, hose0
27-MAR-1997 09:29:53.19 RLIV05 tulip1, slot 6, bus 0, hose0
27-MAR-1997 09:29:57.13 RLIV05 cipca0, slot 6, bus 0, hose1
27-MAR-1997 09:29:57.26 RLIV05 pfi0, slot 11, bus 0, hose1
27-MAR-1997 09:29:57.34 RLIV05 cipca1, slot 6, bus 0, hose4
27-MAR-1997 09:29:57.42 RLIV05 pfi1, slot 11, bus 0, hose4
27-MAR-1997 09:29:57.51 RLIV05 CPU 0 has CPU_TST Disabled in the NVR
27-MAR-1997 09:29:57.53 RLIV05 CPU 1 has CPU_TST Disabled in the NVR
27-MAR-1997 09:29:57.65 RLIV05 CPU 2 has CPU_TST Disabled in the NVR
27-MAR-1997 09:29:57.70 RLIV05 CPU 3 has CPU_TST Disabled in the NVR
27-MAR-1997 09:29:58.17 RLIV05 P00>>>


Ken Robb
CSC Basingstoke

    After a firmware upgrade depending upon the version you upgraded
    from to the version you upgraded to. You must do 
    
     Build -e
    
     Build -n
    
    For each and every CPU node (IE 0,2,4...)
    
    Please be sure to save boot defaults etc. as this data will be lost.
    
    
    
    					/Dave
    

Dave,

Many thanks for the info. 
I have only just come back from holidays, which is why I took so long to get
back to you.

Regards,

Ken.