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| Title: | TurboLaser Notesfile - AlphaServer 8200 and 8400 systems |
| Notice: | Welcome to WONDER::TURBOLASER in it's new home shortly |
| Moderator: | LANDO::DROBNER |
|
| Created: | Tue Dec 20 1994 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 1218 |
| Total number of notes: | 4645 |
1150.0. "Too much simm failure?" by ROMTSS::MATTACCHIONE () Wed Mar 26 1997 06:27
Hi,
our customer have an 8440 that from 3 mounths give ecc memory error
every 2-3 weeks.
The problem appears on different memory nodes and different simm location.
Should be a "normal problem" or is better investigate in other
areas ?
System is in a thrucluster configuration with another 8440 that don't have
this problem.
Operating System version 3.2g.
I have ever replaced the bad module.
Follow the last two decevent report about .
Thanks for your suggestions.
Gabriele
DECevent V2.2
******************************** ENTRY 395 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 122.
Timestamp of occurrence 11-MAR-1997 12:16:27
Host name osra03
System type register x0000000C AlphaServer 8x00
Number of CPUs (mpnum) x00000006
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 4. 620 System Correctable Error
--TLaser 620 Corr Error--
Software Flags x00000001 TLSB Error Log Snapshot Packet Present
Active CPUs x0000003F
Hardware Rev x00000000
System Serial Number qv
Module Serial Number AY64100155
System Revision x00000000
MCHK Reason Mask x00000086
MCHK Frame Rev x00000001
EI STAT xFFFFFFF0C1FFFFFF
DATA SOURCE IS MEMORY OR SYSTEM
CORRECTABLE ECC ERROR
D-ref fill
EI ADDRESS xFFFFFF00D301943F
FILL SYNDROME x0000000000008F00
Data Bit = 112
ISR x0000000100100000
Ext. HW interrupt at IPL20
Correctable ECC errors (IPL31)
AST requests 3 - 0 x0000000000000000
WHAMI x00 TLSB NODE ID 0.
CPU0
MISCR x5D B-Cache Size 4 Mbyte Bcache
Two Processors
TLSB Secure Signal
TLSB RUN Signal
CPU0 Running console
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00840000 CORRECTABLE READ DATA ERROR
DATA SYNDROME 3
TLESR0 x00400303
TLESR1 x00400C0C
TLESR2 x00406060
TLESR3 x00608F00 ECC Syndrome 0 x00000000
ECC Syndrome 1 x0000008F
CORRECTABLE READ ECC ERROR
Error Syndrome 0 x00 No Error
Error Syndrome 1 x8F Data Bit = 240
Palcode Revision x0000000400000400
Palcode Rev: 4.0-1
*TLaser CPU Registers*
TLSB Node Number 0.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00840000 CORRECTABLE READ DATA ERROR
DATA SYNDROME 3
TLCNR x00000200
TLVID x00000010
TLESR0 x00400303
TLESR1 x00400C0C
TLESR2 x00406060
TLESR3 x00608F00 ECC Syndrome 0 x00000000
ECC Syndrome 1 x0000008F
CORRECTABLE READ ECC ERROR
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x000000FE IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
CPU Halt Enable
TLEP Interrupt Summary 0 x00000000
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000000
*TLaser CPU Registers*
TLSB Node Number 1.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00800000
TLCNR x00000210
TLVID x00000032
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00408F00
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x000000FE IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
CPU Halt Enable
TLEP Interrupt Summary 0 x00000000
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000000
*TLaser CPU Registers*
TLSB Node Number 2.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00800000
TLCNR x00000220
TLVID x00000054
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00408F00
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x000000FE IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
CPU Halt Enable
TLEP Interrupt Summary 0 x00000000
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000000
* TLaser Memory Regs *
TLSB Node Number 6.
TLDEV x00005000 -- Device Type: Memory Module
TLBER x00100000
TLCNR x000FC260
TLVID x00000080
FADR 0 x000500000011D680
FADR 1 x00050000
TLESR0 x00000303
TLESR1 x00000C0C
TLESR2 x00006060
TLESR3 x00009090
TMIR x80000001 Interleave x00000001
TMCR x0000022D 2GB Module (E2036-AA)
16 MB
70ns DRAM
Strings Installed = 8
DRAM timing: Bus Spd = 11.3-12.9;
Refresh Cnt = 1088
TMER x00000002 Failing String = x00000002
TMDRA x00000000 Refresh Rate 1X
TDDR0 x00000000
TDDR1 x00000000
TDDR2 x00000000
TDDR3 x00000000
* TLaser Memory Regs *
TLSB Node Number 7.
TLDEV x00005000 -- Device Type: Memory Module
TLBER x01840000 CORRECTABLE READ DATA ERROR
DATA SYNDROME 3
DATA TRANSMITTER DURING ERROR
TLCNR x000FC270
TLVID x00000091
FADR x07120000D3019400
FADR 1 x07120000 Failing Command: Read
Failing Bank = Bank 1
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00218F00 ECC Syndrome 0 x00000000
ECC Syndrome 1 x0000008F
TRANSMITTER DURING ERROR
CORRECTABLE READ ECC ERROR
ECC Code x00
Second ECC Code x8F Failing SIMM Number = J22
TMIR x80000001 Interleave x00000001
TMCR x0000022D 2GB Module (E2036-AA)
16 MB
70ns DRAM
Strings Installed = 8
DRAM timing: Bus Spd = 11.3-12.9;
Refresh Cnt = 1088
TMER x00000000 Failing String = x00000000
TMDRA x00000000 Refresh Rate 1X
TDDR0 x00000000
TDDR1 x00000000
TDDR2 x00000000
TDDR3 x00000000
* TLaser I/O Registers *
TLSB Node Number 8.
TLDEV x00002000 -- Device Type: I/O Module
TLBER x00800000
FADR 0 x0000000000000000
FADR 1 x00000000
TLESR0 x00000000
TLESR1 x00000000
TLESR2 x00000000
TLESR3 x00000000
CPU Interrupt Mask x00000001 Cpu Interrupt Mask = x00000001
ICCMSR x00000000 Arbitration Control Minimum Latency Mode
Supress Control Suppress after 16
Transations
ICCNSE x80000000 Interrupt Enable on NSES Set
ICCMTR x00000000
IDPNSE-0 x00000006 Hose Power OK
Hose Cable OK
IDPNSE-1 x00000006 Hose Power OK
Hose Cable OK
IDPNSE-2 x00000000
IDPNSE-3 x00000000
IDPVR x00000800
ICCWTR x00000000
TLMBPR x0000000000000000
IDPDR0 x20000000
IDPDR1 x20000000
IDPDR2 x00000000
IDPDR3 x00000000
******************************** ENTRY 396 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 121.
Timestamp of occurrence 11-MAR-1997 12:16:24
Host name osra03
System type register x0000000C AlphaServer 8x00
Number of CPUs (mpnum) x00000006
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 4. 620 System Correctable Error
--TLaser 620 Corr Error--
Software Flags x00000001 TLSB Error Log Snapshot Packet Present
Active CPUs x0000003F
Hardware Rev x00000000
System Serial Number qv
Module Serial Number AY64100155
System Revision x00000000
MCHK Reason Mask x00000086
MCHK Frame Rev x00000001
EI STAT xFFFFFFF0C1FFFFFF
DATA SOURCE IS MEMORY OR SYSTEM
CORRECTABLE ECC ERROR
D-ref fill
EI ADDRESS xFFFFFF00D302D43F
FILL SYNDROME x0000000000008F00
Data Bit = 112
ISR x0000000100000000
Correctable ECC errors (IPL31)
AST requests 3 - 0 x0000000000000000
WHAMI x00 TLSB NODE ID 0.
CPU0
MISCR x5D B-Cache Size 4 Mbyte Bcache
Two Processors
TLSB Secure Signal
TLSB RUN Signal
CPU0 Running console
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00840000 CORRECTABLE READ DATA ERROR
DATA SYNDROME 3
TLESR0 x00400303
TLESR1 x00400C0C
TLESR2 x00406060
TLESR3 x00608F00 ECC Syndrome 0 x00000000
ECC Syndrome 1 x0000008F
CORRECTABLE READ ECC ERROR
Error Syndrome 0 x00 No Error
Error Syndrome 1 x8F Data Bit = 240
Palcode Revision x0000000400000400
Palcode Rev: 4.0-1
*TLaser CPU Registers*
TLSB Node Number 0.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00840000 CORRECTABLE READ DATA ERROR
DATA SYNDROME 3
TLCNR x00000200
TLVID x00000010
TLESR0 x00400303
TLESR1 x00400C0C
TLESR2 x00406060
TLESR3 x00608F00 ECC Syndrome 0 x00000000
ECC Syndrome 1 x0000008F
CORRECTABLE READ ECC ERROR
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x000000FE IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
CPU Halt Enable
TLEP Interrupt Summary 0 x00000000
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000000
*TLaser CPU Registers*
TLSB Node Number 1.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00800000
TLCNR x00000210
TLVID x00000032
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00408F00
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x000000FE IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
CPU Halt Enable
TLEP Interrupt Summary 0 x00000000
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000000
*TLaser CPU Registers*
TLSB Node Number 2.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00800000
TLCNR x00000220
TLVID x00000054
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00408F00
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x000000FE IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
CPU Halt Enable
TLEP Interrupt Summary 0 x00000000
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000000
* TLaser Memory Regs *
TLSB Node Number 6.
TLDEV x00005000 -- Device Type: Memory Module
TLBER x00100000
TLCNR x000FC260
TLVID x00000080
FADR 0 x000500000011D680
FADR 1 x00050000
TLESR0 x00000303
TLESR1 x00000C0C
TLESR2 x00006060
TLESR3 x00009090
TMIR x80000001 Interleave x00000001
TMCR x0000022D 2GB Module (E2036-AA)
16 MB
70ns DRAM
Strings Installed = 8
DRAM timing: Bus Spd = 11.3-12.9;
Refresh Cnt = 1088
TMER x00000002 Failing String = x00000002
TMDRA x00000000 Refresh Rate 1X
TDDR0 x00000000
TDDR1 x00000000
TDDR2 x00000000
TDDR3 x00000000
* TLaser Memory Regs *
TLSB Node Number 7.
TLDEV x00005000 -- Device Type: Memory Module
TLBER x01840000 CORRECTABLE READ DATA ERROR
DATA SYNDROME 3
DATA TRANSMITTER DURING ERROR
TLCNR x000FC270
TLVID x00000091
FADR x07120000D302D400
FADR 1 x07120000 Failing Command: Read
Failing Bank = Bank 1
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00218F00 ECC Syndrome 0 x00000000
ECC Syndrome 1 x0000008F
TRANSMITTER DURING ERROR
CORRECTABLE READ ECC ERROR
ECC Code x00
Second ECC Code x8F Failing SIMM Number = J22
TMIR x80000001 Interleave x00000001
TMCR x0000022D 2GB Module (E2036-AA)
16 MB
70ns DRAM
Strings Installed = 8
DRAM timing: Bus Spd = 11.3-12.9;
Refresh Cnt = 1088
TMER x00000000 Failing String = x00000000
TMDRA x00000000 Refresh Rate 1X
TDDR0 x00000000
TDDR1 x00000000
TDDR2 x00000000
TDDR3 x00000000
* TLaser I/O Registers *
TLSB Node Number 8.
TLDEV x00002000 -- Device Type: I/O Module
TLBER x00800000
FADR 0 x0000000000000000
FADR 1 x00000000
TLESR0 x00000000
TLESR1 x00000000
TLESR2 x00000000
TLESR3 x00000000
CPU Interrupt Mask x00000001 Cpu Interrupt Mask = x00000001
ICCMSR x00000000 Arbitration Control Minimum Latency Mode
Supress Control Suppress after 16
Transations
ICCNSE x80000000 Interrupt Enable on NSES Set
ICCMTR x00000000
IDPNSE-0 x00000006 Hose Power OK
Hose Cable OK
IDPNSE-1 x00000006 Hose Power OK
Hose Cable OK
IDPNSE-2 x00000000
IDPNSE-3 x00000000
IDPVR x00000800
ICCWTR x00000000
TLMBPR x0000000000000000
IDPDR0 x20000000
IDPDR1 x20000000
IDPDR2 x00000000
IDPDR3 x00000000
()()()()()()()()()()()()()()
DECevent V2.2
******************************** ENTRY 157 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 1.
Timestamp of occurrence 25-MAR-1997 08:50:44
Host name osra03
System type register x0000000C AlphaServer 8x00
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 4. 620 System Correctable Error
--TLaser 620 Corr Error--
Software Flags x00000001 TLSB Error Log Snapshot Packet Present
Active CPUs x00000001
Hardware Rev x00000000
System Serial Number qv
Module Serial Number AY64100155
System Revision x00000000
MCHK Reason Mask x00000086
MCHK Frame Rev x00000001
EI STAT xFFFFFFF0C1FFFFFF
DATA SOURCE IS MEMORY OR SYSTEM
CORRECTABLE ECC ERROR
D-ref fill
EI ADDRESS xFFFFFF00FE130C4F
FILL SYNDROME x0000000000005400
Data Bit = 099
ISR x0000000100000000
Correctable ECC errors (IPL31)
AST requests 3 - 0 x0000000000000000
WHAMI x00 TLSB NODE ID 0.
CPU0
MISCR x55 B-Cache Size 4 Mbyte Bcache
Two Processors
TLSB RUN Signal
CPU0 Running console
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00240410 NO ACKNOWLEDGE ERROR
ADDRESS TRANSMITTER DURING ERROR
CORRECTABLE READ DATA ERROR
DATA SYNDROME 1
TLESR0 x00400303
TLESR1 x00A00054 ECC Syndrome 0 x00000054
ECC Syndrome 1 x00000000
CORRECTABLE READ ECC ERROR
Error Syndrome 0 x54 Data Bit = 099
Error Syndrome 1 x00 No Error
TLESR2 x00406060
TLESR3 x00409090
Palcode Revision x0000000400000400
Palcode Rev: 4.0-1
*TLaser CPU Registers*
TLSB Node Number 0.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00240410 NO ACKNOWLEDGE ERROR
ADDRESS TRANSMITTER DURING ERROR
CORRECTABLE READ DATA ERROR
DATA SYNDROME 1
TLCNR x00000200
TLVID x00000010
TLESR0 x00400303
TLESR1 x00A00054 ECC Syndrome 0 x00000054
ECC Syndrome 1 x00000000
CORRECTABLE READ ECC ERROR
TLESR2 x00406060
TLESR3 x00409090
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x0000007E IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
TLEP Interrupt Summary 0 x00000000
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000040 Interval Timer Interrupt Outstanding
*TLaser CPU Registers*
TLSB Node Number 1.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00800000
TLCNR x00000210
TLVID x00000032
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00000303
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x0000007E IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
TLEP Interrupt Summary 0 x00000040 Interval Timer Interrupt Outstanding
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000040 Interval Timer Interrupt Outstanding
*TLaser CPU Registers*
TLSB Node Number 2.
TLDEV x73008014 -- Device Type: Dual EV56 Proc, 440Mhz,
4meg Bcache
TLBER x00800000
TLCNR x00000220
TLVID x00000054
TLESR0 x00000303
TLESR1 x00000303
TLESR2 x00000303
TLESR3 x00000303
TLEPAERR x00600000 Second ADG Design: Rev A
MODCONFIG x00E08A84 Bcache Size: 4 MB
Bcache Idle Cycles Before 10.
Max Command Queue Entries 2.
Max Bus Queue Entries 4.
TLEPMERR x00000000
TLEPDERR x00000000
TLEP Interrupt Mask 0 x0000007E IPL 14 Interrupt Enable
IPL 15 Interrupt Enable
IPL 16 Interrupt Enable
IPL 17 Interrupt Enable
Interprocessor Interrupt Enable
Interval Timer Interrupt Enable
TLEP Interrupt Summary 0 x00000040 Interval Timer Interrupt Outstanding
TLEP Interrupt Mask 1 x00000000
TLEP Interrupt Summary 1 x00000040 Interval Timer Interrupt Outstanding
* TLaser Memory Regs *
TLSB Node Number 6.
TLDEV x00005000 -- Device Type: Memory Module
TLBER x00100000
TLCNR x000FC260
TLVID x00000080
FADR x070500000011D680
FADR 1 x07050000 Failing Command: Write Bank Unlock
Failing Bank = Bank 0
TLESR0 x00000303
TLESR1 x00000C0C
TLESR2 x00006060
TLESR3 x00009090
TMIR x80000001 Interleave x00000001
TMCR x0000022D 2GB Module (E2036-AA)
16 MB
70ns DRAM
Strings Installed = 8
DRAM timing: Bus Spd = 11.3-12.9;
Refresh Cnt = 1088
TMER x00000002 Failing String = x00000002
TMDRA x00000000 Refresh Rate 1X
TDDR0 x00000000
TDDR1 x00000000
TDDR2 x00000000
TDDR3 x00000000
* TLaser Memory Regs *
TLSB Node Number 7.
TLDEV x00005000 -- Device Type: Memory Module
TLBER x01240000 CORRECTABLE READ DATA ERROR
DATA SYNDROME 1
DATA TRANSMITTER DURING ERROR
TLCNR x000FC270
TLVID x00000091
FADR x07920000FE130C40
FADR 1 x07920000 Failing Command: Read
Failing Bank = Bank 9
TLESR0 x00000303
TLESR1 x00210054 ECC Syndrome 0 x00000054
ECC Syndrome 1 x00000000
TRANSMITTER DURING ERROR
CORRECTABLE READ ECC ERROR
ECC Code x54 Failing SIMM Number = J05
Second ECC Code x00
TLESR2 x00000303
TLESR3 x00000303
TMIR x80000001 Interleave x00000001
TMCR x0000022D 2GB Module (E2036-AA)
16 MB
70ns DRAM
Strings Installed = 8
DRAM timing: Bus Spd = 11.3-12.9;
Refresh Cnt = 1088
TMER x00000001 Failing String = x00000001
TMDRA x00000000 Refresh Rate 1X
TDDR0 x00000000
TDDR1 x00000000
TDDR2 x00000000
TDDR3 x00000000
* TLaser I/O Registers *
TLSB Node Number 8.
TLDEV x00002000 -- Device Type: I/O Module
TLBER x00000000
FADR 0 x0000000000000000
FADR 1 x00000000
TLESR0 x00000000
TLESR1 x00000000
TLESR2 x00000000
TLESR3 x00000000
CPU Interrupt Mask x00000001 Cpu Interrupt Mask = x00000001
ICCMSR x00000000 Arbitration Control Minimum Latency Mode
Supress Control Suppress after 16
Transations
ICCNSE x00000000
ICCMTR x00000000
IDPNSE-0 x00000006 Hose Power OK
Hose Cable OK
IDPNSE-1 x00000006 Hose Power OK
Hose Cable OK
IDPNSE-2 x00000000
IDPNSE-3 x00000000
IDPVR x00000800
ICCWTR x00000000
TLMBPR x0000000000000000
IDPDR0 x20000000
IDPDR1 x20000000
IDPDR2 x00000000
IDPDR3 x00000000
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