| Title: | TurboLaser Notesfile - AlphaServer 8200 and 8400 systems |
| Notice: | Welcome to WONDER::TURBOLASER in it's new home shortly |
| Moderator: | LANDO::DROBNER |
| Created: | Tue Dec 20 1994 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 1218 |
| Total number of notes: | 4645 |
I'm configuring a 8400 with 108 RZ28's. We're spreading them evenly
across (6) HSZ50/KZPSA's ( 18 drives per HSZ50, RAID5 ).
The customer is very concerned about I/O performance, especially
IO's/sec. He is currently seeing a maximum of 1300 IO's/sec but expect
that to rapidly increase to 2000.
Because of this, we are considering several scenarios:
1. (1) KFTIA with 1 DWLPA,using 2-Integrated FWD controllers and 4-KZPSA's
2. (1) KFTHA with 2-DWLPA's, 3-KZPSA's per DWLPA.
3. (2) KFTIA's , using all 6 Integrated FWD controllers (No DWLPA's)
OR 1-DWLPA per KFTIA and 3-KZPSA's per DWLPA
What is the preferred config to maximize IO's per sec ?
What are pros, cons of these scenarios ?
What is the maximum IO's per sec for a KFTIA or KFTHA ??
Thx,
Dave Rifkin
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 1074.1 | WASHDC::RKLING | Fri Jan 31 1997 14:10 | 5 | ||
It would be nice if in answering this question someone would give an indication of what the sustained bandwidth of the DWLPBs are and whether or not this is an aggregate bandwidth across the 3 pci buses within the DWLPB. Thanks | |||||
| 1074.2 | Try via email ... | I4GET::HENNING | Mon Feb 03 1997 06:32 | 7 | |
There is at least one person in our group who seems to know some
answers but who does not want to go on definitive public record with
them. Perhaps it's an instance of "Experimenter's Good Intuition"
rather than official data.
Send a query to PERFOM::CSGPERF, or to [email protected], or click on
"Ask the perf group" under http://sdtad.zko.dec.com/pub/csdpg/
| |||||
| 1074.3 | 105 MMB/s | WONDER::WILLARD | Tue Feb 04 1997 19:10 | 19 | |
re .1: > It would be nice if in answering this question someone would > give an indication of what the sustained bandwidth of the > DWLPBs are and whether or not this is an aggregate bandwidth across the 3 pci buses within the DWLPB. DWLPx bandwidth has been discussed elsewhere in this notesfile; see note 54.* The short answer is up to 105 MB/s per DWLPx, assuming that only well-designed PCI widgets are used. But, the widgets that you probably plan to use won't fit the definition of well-designed, and neither you nor I will know how much any given widget will cause real bandwidth to dip below the 105 MB/s upper bound without connecting the widget(s) to the DWLPx with the real glue of software. Cheers, Bob | |||||