Conference turris::digital_unix

9336.0. "TPC-C benchmark and the Alpha cache architecture" by VAXRIO::LEO () Mon Mar 31 1997 18:49

    Hi,
    
    I would like to know how important is the several levels and sizes of
    processor and external caches in order to achieve high TPC-C numbers ?
    
    I have posted this note on this conference because I think that TPC-C
    is a very important benchmark wich is used by the technical press and
    customers to evaluate the best Operating System and platform in terms
    of commercial applications.
    
    
    1) Data and Instrution processor caches
    
    How the data and instruction processor caches are really used in this 
    benchmark ?
    
    The EV5 has an internal cache of 112 KB. 
    
    8 KB of data + 8 KB of instructions -> first cache
    
    96 KB (data and instructions) -> second cache
    
    Are the additional 96 KB so fast as the ORIGINAL 16 KB ?
    
    What is the average time to access an info inside the 16 KB cache ?
    
    What is the average time to access an info inside the 96 KB cache ?
    
    Is the size of the fist data and instruction cache a limitation comparing 
    against HP and SUN ?
    
    HP 9000 Model K460 Enterprise Server has achieved 14,739.03 tpmC with 4
    180 MHZ PA-RISC 8000 1 MB Instruction cache, 1 MB Data cache. HP has
    used 4GB of RAM and 919 GB of disks (46 HP AutoRaid with 12 2.0 GB disk 
    drives). This number is almost the half of the 30,390 tpmC result
    achieved by the 32 CPUs 4-node cluster compound of 8400 5/350. 
    
  -> The only thing in the above configuration that Alpha cannot be bigger is
     the instruction and data cache .
    
    SUN Ultra Enterprise 6000 has achieved 23,143.65 tpmC with 16 250 MHZ
    UltraSPARC 32KB (D+I), 4MB external. SUN has used 5 GB of RAM and
    2167.2 GB of disks (18 SparcStorage Array's Model 114, 30 4.2GB SCSI in 
    17 SparcStorage Arrays and 6 4.2 GB SCSI in 1 SparcStorage Array).
    This is a very good number. They are not using cluster and just using
    16 CPUs (perhaps more CPUs would generate contention...but the customer
    sometimes don't want to know about good scalability ...)
    
  -> The only way to have more than 16 KB of data and instruction cache is
     to consider the use of the second (mixed) Alpha data/instruction 96 kb 
     cache. SUN like HP has just one level of data and instruction cache.
     As we see in the above configuration SUN has a 32 KB (d+i) cache.
    
     Is there any performance problem regarding the TPC-C benchmark when 
     using two levels of data and instruction caches ? And what about their
     sizes is there any limitation imposed by the Alpha 16 KB fisrt level 
     implementation ?
    
     Is that rigth to call the first 16 KB as "the fisrt level of data and
     instructions cache" an the others 96 kb (mixed) as "the second level of 
     data and instructions cache ? 
    
    2) External cache
    
    SUN has jumped from 18,438.70 tmpC to 23,143.65 tmpC. On both tests SUN
    has used a Ultra Enterprise 6000 with 5GB of RAM. In the fisrt test SUN 
    has used 20 250 MHZ UltraSparc. In the second one SUN has used just 16
    250 MHZ UltraSparc. In the first test SUN has used 610 2.1 GB SCSI
    disks(20 FC25/S and 2 SCSI/2 controllers). In the second one SUN has 
    used 516 4.2 GB SCSI disks (18 FC25/S controllers).
    
    In the first test the operating System was Solaris 2.5.1 in the second
    test it was Solaris 2.6.
    
    The Database was Sybase SQL Server 11.1 in the first benchmark and it
    was Oracle 7 Server v7.3.3 in the second one.
    
    The last and perhaps the most important difference was the size of the
    external cache.
    
    In the first benchmark (18,438.70 tpmC) the size of the external cache
    (not the data and instruction cache) was 1 MB.
    
    In the second benchmark (23,143.65 tpmC) the size of the external cache
    (not the data and instruction cache) was 4 MB.
    
    The difference in number of CPUs and size of disks seems to be
    strategic to make the whole SUN configuration less expensive, in order
    to achieve a better price/performance.
    
    But the new version of Solaris, the use of Oracle 7 and the size of
    external cache seems to have a impressive impact on the overall
    performance of the benchmark.
    
    Is it possible to improve so much the TPC-C benchmark just increasing
    the size of the external cache ? What is the role of the external cache 
    on this benchmark ?
    
    Is that rigth to call the external cache as the "third level cache" ?
    
    What is the average time to access an info in the Alpha external 
    cache ? 
    
    3) Associative memories
    
    Is the associative memory used on all levels of cache or just in the
    first one ?
    
    
    Bottom line, could anyone help me in understanding the real use of processor
    and external caches in a so important benchmark such as TCP-C ?
     
    Are we using the Alpha architecture in any kind of disadvantage
    regarding the processor and external caches ?
    
    
     
    As far as I know TPC-C is a benchmark compound of 5 very differents
    types of transactions with much more complexity than the obsoletes
    TPC-A and TPC-B. Is ist possible that this benchmark fits better in 
    platforms with bigger processor and external caches ?
    
    In this case external caches would not be a problem for Alpha machines 
    but increasing the data and instruction cache would represent a very big 
    callenge.
    
    Any help or pointer would be very appreciated.
    
    Best regards,
    
    Leo
    
    Digital Technical Support
    Brazil
    
    
    

    see RICKS::DECHIPS notes 571.40 and 659.*
    
    Hugh