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I fixed the problem I was having. What is interesting, is that
the new EV56 enhanced interfaces brought it out. Part of our
initialization of our PCI bus adapter, had us do writes to the
PCI_CONFIG space of our PCI device. One of the two writes, was
a word access to the Latency register (offset 0x0D) and Header
Type register (offset 0x0E). The Latency and Header registers
are 8-bit registers. On older platforms, this code worked just
fine. On the EV56, I crashed with an "unaligned kernel access".
I then ran the EV56 Brett (DUNIX 4.0A) in EV5 mode. This was done
by setting ev56_bw_io_maps=0 at boot time. Using a PCI bus
analyzer I saw my word write happen just fine. Then I ran it
under normal for Brett (EV56 mode) and the PCI analyzer shows the
this word write never occurring (system crashes). I then tried to do
the writes as seperate BYTE accesses and all worked great under
normal EV56 mode.
It appears the EV56-Brett will not let you do a word access to two
adjacent byte registers in PCI config space. To do the actual
write, I call the pci_sw table config_fcn for the platform I am
on. This call eventually makes a write_io_port call. In the Brett
platform code, the write_io_port has different code paths for
EV56 and non-EV56 systems. The above variable tells this call
which path to take.
This is not bad, just different behavior than before.
This was a platform - Brett configuration write function as well.
So behavior on other EV56 platforms may be different.
Enjoy, Tim
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To complete this note path...
The UNIX engineering group was very helpful and provided me with
the reason for the behavior I saw.
The "word" writes I was doing to PCI config space were NOT word
address aligned. The new linear I/O features in the EV56 code
want to be word aligned for word accesses. In the older code
path, the accesses are "sparse" accesses, and since the hardware
alows this, they complete normally.
Thank you all for your input, it is truelly appreciated,
Tim
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