| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 3538.1 | Use reflected clocks at 6M | MARVIN::HIGGINSON | Peter Higginson DTN 830 6293, Reading UK | Thu Feb 13 1997 03:27 | 39 |
|
I've no idea what 3dinverted is - if it's a reference to some encoding
(like HDB3) then thats between the 3800 and the lines and nothing to do
with the DECNIS.
If it works at 6M then the DECNIS end is probably ok.
In all cases, particularly when it fails, what does the DECNIS measure
the "actual speed" as and what are the error counters (ncl sho mod conn
lin * all).
Does it fail when any T1 is removed or only the first one (a customer did
have that problem in the 3800)?
===============================================================================
From my reply to your previous posting, discussing the clocks between
3800 and the DECNIS and the only use of inverted I've come accross:
In normal circumstances, with fixed speed clocks, it only matters
to find a stable part of the clock to trigger off. A common trick
is to use inverted clocks to sample one half bit late in order to
get a stable part of the data signal.
With variable speed clocks late sampling is a disaster because if
it works at 6M, it will be exactly wrong at 3M (because half a bit
is now a bit time).
Hence you must use short cable lengths and reflected clocks at 6M.
Apart from really making sure that it is a 622HS card - see if it
can measure the clock speed accurately don't trust the label - all
the other problems we have had have been down to Digital Link.
Were the T1 lines all ordered together? (clock and/or analogue/digital
mixtures have caused problems).
Peter
|
| 3538.2 | only problem at 4.5 meg | PATS::NETWORK | | Thu Feb 13 1997 09:51 | 8 |
| The DECnis gets the right speed but the circuit is not passing data
when we have lost one T1. We have no problem running with 3 T1s, 2 T1s and
1 T1.
You said that there were another case like this, what did you do to fix
it ? Shorter cables ?
Thank you,
/lillemro
|
| 3538.3 | | MARVIN::HIGGINSON | Peter Higginson DTN 830 6293, Reading UK | Thu Feb 13 1997 13:29 | 15 |
|
There is (or should be) no difference from the DECNIS point of view
between 3 T1's and 4 T1's with one down.
Hence this is a DL 3800 problem.
2nd hand from a customer went something like "The DL 3800 takes it's
clock from the 1st T1 and wasn't able to cope when other T1's had
clocks from different sources or the first T1 was lost"
(Anyone from the CSC remember any more about this??)
Is the actual speed in the cases "3 T1's" and "4 T1's with one down" the same?
Peter
|
| 3538.4 | | PATS::NETWORK | | Thu Feb 13 1997 17:01 | 2 |
| We had a problem when any of the 4 T1 was down. The circuit is fine at
6meg,3meg, 1.5 meg, problem only at 4.5 meg.
|
| 3538.5 | | MARVIN::HIGGINSON | Peter Higginson DTN 830 6293, Reading UK | Thu Feb 13 1997 17:23 | 6 |
|
But an earlier reply says that 3 T1's is ok - that's 4.5M. I don't see
how the DECNIS can tell the difference - what does it think the speed is?
Peter
|
| 3538.6 | | PATS::NETWORK | | Fri Feb 14 1997 09:05 | 10 |
|
The problem we have is that the decnis do not pass data over the circuit
when 1 T1 out of the 4 T1s is down. The DECnis show the actual speed 4.5
but are not passing data, and after a few minuts we lose adjacency.
We have no problem when we have lost 2 T1s out of 4, actual speed 3meg
and passing data fine, no problem when we have lost 3 T1s out of 4, actual
speed 1.5 meg and passing data.
/lillemor
|