| Title: | DEChub/HUBwatch/PROBEwatch CONFERENCE |
| Notice: | Firmware -2, Doc -3, Power -4, HW kits -5, firm load -6&7 |
| Moderator: | NETCAD::COLELLA DT |
| Created: | Wed Nov 13 1991 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 4455 |
| Total number of notes: | 16761 |
Hi, I have an RFP question which asks what type of bus and speed does the DECswitch 900EF have. This is actually quite interesting. Does the 900EF have a bus or is there some other means of connecting switch ports. Any help appreciated. regards Murray
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 2315.1 | NETCAD::B_CRONIN | Wed May 24 1995 19:35 | 18 | ||
The switch makes use of the DEChub's technology independent backplane
to form either bussed connections in the case of Ethernet, or,
point to point connections in the case of FDDI.
In the Ethernet case, all the modules that wish to connect to an
Ethernet LAN connect to the same backplane channel used for that
LAN. In that sense, a bus has been formed since all of the modules
talk to the same backplane channel.
In the case of the FDDI, each module talks to the next module
over a pair of channels, similar to what happens with optical
FDDI connections.
Other technologies can use the backplane channels in the manner
necessary for that particular technology.
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| 2315.2 | NETCAD::DOODY | Michael Doody | Wed May 24 1995 19:42 | 5 | |
I got the impression they meant internal to the switch, rather than how
it connected to other things in the hub.
?
-Mike
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| 2315.3 | CCOF02::PENNO | Murray Penno | Wed May 24 1995 23:03 | 3 | |
.2 is correct internal to the switch. Murray | |||||
| 2315.4 | Quickee explanation of DECswitch internal Bus structure | NETCAD::BATTERSBY | Thu May 25 1995 10:31 | 13 | |
The DECswitch 900EF has 2 internal processors, a 68EC040 (main
engine) running at 25mhz, and a 68000 (FDDI engine) running at 12.5mhz.
There are 2 proprietary internal buses called a HS Bus (High Speed Bus),
and an IOC Bus.
The HS Bus is used exclusively for 32 bit wide data burst transfers
to and from Main Packet Memory. The IOC Bus is used for general system
control and port ring ring descriptor access, and for port packet
memory descriptors.
The rest of the subsystems are buffered off these 2 main buses.
Bob
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| 2315.5 | NETCAD::ANIL | Thu May 25 1995 20:52 | 5 | ||
I would not make such info available to customer. It is misleading
more than useful. At the most, I would say "multiple motorola
processors with hardware assist and high-speed internal data bus."
Anil
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