| > It appears that the 68000 is asserting reset,(not pulling it down)
> Does anyone know if the 68000 should be able to assert reset and under
> what circumstances
I have the spec doc on the 68000 at home and I remember seeing something
about a reset line and when it does what. I am not much of a hardware
type so I can't be sure I will understand your problem enough to help,
but I will look at home a get back to you.
It sounds like you must know a fair amount about chips, so any info
you can give me on what I'm looking for would help me find it.
Jim Patterson
(just home from 1 1/2 weeks in Italy)
|
| > It appears that the 68000 is asserting reset,(not pulling it down)
> Does anyone know if the 68000 should be able to assert reset and under
> what circumstances
There is a reset instruction that will assert the reset line
for 124 clock cycles. I know that this instruction is in TOS on
disk and TOS 1.0.
The reset line is used bi-directionally to reset the system,
if it is asserted externally, the 68000 read the SSP from memory
location $0000000 and the PC from $00000004, set IPL to 7, turns
supervisor mode, and begin execution.
If the reset line is asserted by the 68000 using the reset
instruction, the rest of the system is supposed to reset.
There is a second line that is often mentioned with the reset,
that is the HALT line.
If you need more info, let me know what it is, and I'll look it
up.
Jim
|