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| Title: | USG buildhelp questions/answers |
|
| Moderator: | SMURF::FILTER |
|
| Created: | Mon Apr 26 1993 |
| Last Modified: | Mon Jan 20 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 2763 |
| Total number of notes: | 5802 |
1972.0. "U/A: v32supportos-193-steinman bdiff and diff does not match" by AOSG::FILTER (Automatic Posting Software - mail to flume::puck) Mon Dec 04 1995 20:24
Date Of Receipt: 4-DEC-1995 14:15:05.47
From: SMURF::ALPHA::"[email protected]" "04-Dec-1995 1407"
To: [email protected]
CC: [email protected], [email protected],
[email protected], [email protected]
Subj: U/A: v32supportos-193-steinman bdiff and diff does not match
There appear to be a problem in the RCS tree. What I check out "bco" and what
I get from the bdiff does not match. Looks like bdiff is missing submits from
1.1.12.4 thru 1.1.26.4. Please investigate this problem as it is preventing a
submit from occurring.
Output from "bdiff -r$NEW -all -c >$ bdiff.log
----------------------------------------------
[ ./kernel/io/dec/eisa/xcr_port.c ]
===================================================================
RCS file: ./kernel/io/dec/eisa/xcr_port.c,v
retrieving revision 1.1.12.4
diff -c -r1.1.12.4 OdeSrvrTmpJohn_Steinman003635/xcr_port.c
*** 1.1.12.4 1994/08/26 15:11:55
--- OdeSrvrTmpJohn_Steinman003635/xcr_port.c 1995/12/04 18:56:18
***************
*** 4,13 ****
/*
* HISTORY
* $Log: xcr_port.c,v $
* Revision 1.1.12.4 1994/08/26 15:11:55 Cheryl_Deleo
* Deleted some debug print statements. Fixed a typo on an error message.
* [1994/08/26 15:10:24 Cheryl_Deleo]
! *
* Revision 1.1.12.3 1994/08/01 21:07:27 Cheryl_Deleo
* Straightened file out after "horrible" merge.
* [1994/08/01 20:10:43 Cheryl_Deleo]
--- 4,30 ----
/*
* HISTORY
* $Log: xcr_port.c,v $
+ * Revision 1.1.35.2 1995/12/04 18:56:03 John_Steinman
+ * Back port of fix for DMO100161 (QAR #39130). Don't panic insert special
+ * command at tail of pending queue when there's no regular I/O and a
special
+ * command(s) already on the queue. - authored by Cheryl_Deleo
+ *
+ * Revision 1.1.26.2 1995/07/19 19:35:34 Jan_Reimers
+ * Ported Revisions 1.1.20.2 and 1.1.15.2 (Caroline_Fleming) from V3.2B
+ * Revision 1.1.20.2 1995/03/08 18:20:01 Caroline_Fleming
+ * Add check to see if proc pointer is a kernel address (QAR#20992). Add
+ * performance enhancement by changing byte read/writes to long word
+ * read/writes.
+ *
+ * Revision 1.1.15.2 1995/02/20 19:59:21 Caroline_Fleming
+ * <<<Add read of last I/O register write to ensure pipe gets flushed on
+ * EV5 systems>>>
+ * [1995/07/07 18:22:00 Jan_Reimers]
+ *
* Revision 1.1.12.4 1994/08/26 15:11:55 Cheryl_Deleo
* Deleted some debug print statements. Fixed a typo on an error message.
* [1994/08/26 15:10:24 Cheryl_Deleo]
! *
* Revision 1.1.12.3 1994/08/01 21:07:27 Cheryl_Deleo
* Straightened file out after "horrible" merge.
* [1994/08/01 20:10:43 Cheryl_Deleo]
***************
*** 62,68 ****
*
* $EndLog$
*/
! #pragma ident "@(#)$RCSfile: xcr_port.c,v $ $Revision: 1.1.12.4 $ (DEC)
$Date: 1994/08/26 15:11:55 $"
#define XCRERRLOG
--- 79,85 ----
*
* $EndLog$
*/
! #pragma ident "@(#)$RCSfile: xcr_port.c,v $ $Revision: 1.1.35.2 $ (DEC)
$Date: 1995/12/04 18:56:03 $"
#define XCRERRLOG
***************
*** 350,355 ****
--- 367,373 ----
WBFLUSH();
WRITE_BUS_D8(xcr_softc->sc_iohandle + PCI_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(xcr_softc->sc_iohandle + PCI_LDBELL);
} else { /* BUS_EISA */
xcr_softc->sc_iohandle = handle;
***************
*** 402,407 ****
--- 420,426 ----
WBFLUSH();
WRITE_BUS_D8(xcr_softc->sc_iohandle + EISA_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(xcr_softc->sc_iohandle + EISA_LDBELL);
}
/*
***************
*** 1204,1212 ****
break;
}
list = list->cntrl_flink;
! }
if( found == 0 ){
! panic("xcr_que_insert list corruption");
}
}
--- 1223,1236 ----
break;
}
list = list->cntrl_flink;
! }
! /*
! * If we didn't find any regular I/O on the queue just
! * insert the "special" command at the tail of the queue
! * (ie. after the other special command(s))...Don't panic
! */
if( found == 0 ){
! XCR_INSERT_PND( xcr_softc, cnt_ws);
}
}
***************
*** 1757,1767 ****
}
/*
! * Map load them...
*/
bc = dma_map_load( sg->xcr_sg_count, (vm_offset_t)sg->xcr_sg_addr,
! procp, softc->sc_ctrl, &ctrl_ws->dma_mapping0, MAXIO,
! dma_flags);
/*
* Make sure we got what we want...
--- 1781,1792 ----
}
/*
! * Map load them... The address is a kernel address
*/
bc = dma_map_load( sg->xcr_sg_count, (vm_offset_t)sg->xcr_sg_addr,
! (!IS_SYS_VA((vm_offset_t)sg->xcr_sg_addr)) ? procp :
! (struct proc *)NULL, softc->sc_ctrl, &ctrl_ws->dma_mapping0,
! MAXIO, dma_flags);
/*
* Make sure we got what we want...
***************
*** 1789,1799 ****
return(XCR_RESOURCE_FAIL);
}
/*
! * Map load them...
*/
bc = dma_map_load( sg->xcr_sg_count, (vm_offset_t)sg->xcr_sg_addr,
! procp, softc->sc_ctrl, &ctrl_ws->dma_mapping1, MAXIO,
! dma_flags);
/*
* Make sure we got what we want...
--- 1814,1825 ----
return(XCR_RESOURCE_FAIL);
}
/*
! * Map load them... Kernel address
*/
bc = dma_map_load( sg->xcr_sg_count, (vm_offset_t)sg->xcr_sg_addr,
! (!IS_SYS_VA((vm_offset_t)sg->xcr_sg_addr)) ? procp :
! (struct proc *)NULL, softc->sc_ctrl, &ctrl_ws->dma_mapping1,
! MAXIO, dma_flags);
/*
* Make sure we got what we want...
***************
*** 1854,1860 ****
*/
bc = dma_map_load( num_sg * sizeof(DMA_SG_LIST),
(vm_offset_t)ctrl_ws->cntrl_dma,
! procp, softc->sc_ctrl, &ctrl_ws->dma_mapping_sg, MAXIO,
dma_flags);
/*
--- 1880,1888 ----
*/
bc = dma_map_load( num_sg * sizeof(DMA_SG_LIST),
(vm_offset_t)ctrl_ws->cntrl_dma,
! (!IS_SYS_VA((vm_offset_t)ctrl_ws->cntrl_dma)) ? procp :
! (struct proc *)NULL, softc->sc_ctrl,
! &ctrl_ws->dma_mapping_sg, MAXIO,
dma_flags);
/*
***************
*** 1920,1926 ****
* Map load them...
*/
bc = dma_map_load( sizeof( XCR_SCSICMD),
! (vm_offset_t)com->xcr_cmd_data, procp,
softc->sc_ctrl, &ctrl_ws->dma_mapping0, MAXIO, dma_flags);
/*
--- 1948,1956 ----
* Map load them...
*/
bc = dma_map_load( sizeof( XCR_SCSICMD),
! (vm_offset_t)com->xcr_cmd_data,
! (!IS_SYS_VA((vm_offset_t)com->xcr_cmd_data)) ? procp :
! (struct proc *)NULL,
softc->sc_ctrl, &ctrl_ws->dma_mapping0, MAXIO, dma_flags);
/*
***************
*** 1957,1963 ****
*/
bc = dma_map_load( com->xcr_dxfer_len,
(vm_offset_t)com->xcr_data_ptr,
! procp, softc->sc_ctrl, &ctrl_ws->dma_mapping1,
MAXIO, dma_flags);
/*
--- 1987,1995 ----
*/
bc = dma_map_load( com->xcr_dxfer_len,
(vm_offset_t)com->xcr_data_ptr,
! (!IS_SYS_VA((vm_offset_t)com->xcr_data_ptr)) ? procp :
! (struct proc *)NULL, softc->sc_ctrl,
! &ctrl_ws->dma_mapping1,
MAXIO, dma_flags);
/*
***************
*** 2006,2012 ****
*/
bc = dma_map_load( com->xcr_dxfer_len,
(vm_offset_t)com->xcr_data_ptr,
! procp, softc->sc_ctrl, &ctrl_ws->dma_mapping0,
MAXIO, dma_flags);
/*
--- 2038,2046 ----
*/
bc = dma_map_load( com->xcr_dxfer_len,
(vm_offset_t)com->xcr_data_ptr,
! (!IS_SYS_VA((vm_offset_t)com->xcr_data_ptr)) ? procp :
! (struct proc *)NULL, softc->sc_ctrl,
! &ctrl_ws->dma_mapping0,
MAXIO, dma_flags);
/*
***************
*** 2053,2059 ****
* Map load them...
*/
bc = dma_map_load( com->xcr_dxfer_len,
! (vm_offset_t)com->xcr_data_ptr, procp,
softc->sc_ctrl, &ctrl_ws->dma_mapping0, MAXIO, dma_flags);
/*
--- 2087,2095 ----
* Map load them...
*/
bc = dma_map_load( com->xcr_dxfer_len,
! (vm_offset_t)com->xcr_data_ptr,
! (!IS_SYS_VA((vm_offset_t)com->xcr_data_ptr)) ? procp :
! (struct proc *)NULL,
softc->sc_ctrl, &ctrl_ws->dma_mapping0, MAXIO, dma_flags);
/*
***************
*** 2115,2121 ****
*/
bc = dma_map_load( num_sg * sizeof(DMA_SG_LIST),
(vm_offset_t)ctrl_ws->cntrl_dma,
! procp, softc->sc_ctrl, &ctrl_ws->dma_mapping_sg, MAXIO,
dma_flags);
/*
--- 2151,2159 ----
*/
bc = dma_map_load( num_sg * sizeof(DMA_SG_LIST),
(vm_offset_t)ctrl_ws->cntrl_dma,
! (!IS_SYS_VA((vm_offset_t)ctrl_ws->cntrl_dma)) ? procp :
! (struct proc *)NULL,
! softc->sc_ctrl, &ctrl_ws->dma_mapping_sg, MAXIO,
dma_flags);
/*
***************
*** 2285,2292 ****
--- 2323,2332 ----
* set the bit to tell the controller to restart
*/
WRITE_BUS_D8(softc->sc_iohandle + EISA_DBELL, 0x2);
+ WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, 0x10);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
/*
* Now we have tp wait up to 5 seconds for the bit to clear.
*/
***************
*** 2362,2367 ****
--- 2402,2408 ----
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
/*
* We are suppose to delay 75ms then wait for upto 2 minutes
***************
*** 2430,2435 ****
--- 2471,2477 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + EISA_DBELL, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_DBELL);
/*
* Check to see if controller is dead.
***************
*** 2452,2457 ****
--- 2494,2500 ----
if( result & XCR_DRV_SEQ ){
WRITE_BUS_D8(softc->sc_iohandle + EISA_DBELL, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_DBELL);
/*
* We must now wait for another 2 minutes..
*/
***************
*** 2498,2503 ****
--- 2541,2547 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
}
***************
*** 2508,2513 ****
--- 2552,2558 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + EISA_SYS_INTR, XCR_INTR_ENABLE);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_SYS_INTR);
XCR_UNLCK_REG(softc, spl );
***************
*** 2559,2564 ****
--- 2604,2610 ----
CNTRL_WS *cnt_ws; /* Pointer to the controller working
set */
CMD_QUE *slot; /* Pointer to the cmd que slot. */
int spl, spl1;
+ u_int tmp;
u_char id, status1, status2; /* our register that we read */
static u_char module[] = "xcrintr";
***************
*** 2596,2604 ****
--- 2642,2657 ----
/*
* It interrupted us now get the registers we need...
*/
+ /*
id = READ_BUS_D8( softc->sc_iohandle + XCR_MBXD );
status1 = READ_BUS_D8( softc->sc_iohandle + XCR_MBXE );
status2 = READ_BUS_D8( softc->sc_iohandle + XCR_MBXF );
+ */
+
+ /*
+ * Do it on a 32 bit boundary
+ */
+ tmp = READ_BUS_D32( softc->sc_iohandle + XCR_MBXC);
/*
* Now dismiss this interrupt
***************
*** 2607,2616 ****
--- 2660,2681 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
XCR_UNLCK_REG(softc, spl);
/*
+ * Now get the results
+ * id is in bits 8 - 15
+ * status1 bits 16 - 23
+ * status2 bits 24 - 31
+ */
+ id = ((tmp >> 8) & 0xff);
+ status1 = ((tmp >> 16) & 0xff);
+ status2 = ((tmp >> 24) & 0xff);
+
+
+ /*
* Get the address of the command slot
* Make sure that it was active then clear the active bit
*/
***************
*** 2698,2705 ****
--- 2763,2772 ----
* set the bit to tell the controller to restart
*/
WRITE_BUS_D8(softc->sc_iohandle + EISA_DBELL, 0x2);
+ WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, 0x10);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
/*
* Now we have tp wait up to 5 seconds for the bit to clear.
*/
***************
*** 2776,2781 ****
--- 2843,2849 ----
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
/*
* We are suppose to delay 75ms then wait for upto 2 minutes
* for the bit to clear.. We are going to do this in one step.
***************
*** 2837,2842 ****
--- 2905,2911 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + EISA_DBELL, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_DBELL);
/*
* Check to see if controller is dead.
***************
*** 2859,2864 ****
--- 2928,2934 ----
if( result & XCR_DRV_SEQ ){
WRITE_BUS_D8(softc->sc_iohandle + EISA_DBELL, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_DBELL);
/*
* We must now wait for another 2 minutes..
*/
***************
*** 2906,2911 ****
--- 2976,2982 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
}
***************
*** 2916,2921 ****
--- 2987,2993 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + EISA_SYS_INTR, XCR_INTR_ENABLE);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_SYS_INTR);
XCR_UNLCK_REG(softc, spl );
***************
*** 2958,2963 ****
--- 3030,3036 ----
{
XCR_SOFTC *softc = ctrl_ws->cntrl_softc;
int spl, spl1;
+ u_int *tmp_ptr=(u_int *)NULL;
int spin_cnt = 0;
static u_char module[] = "xcr_do_cmd";
***************
*** 3027,3032 ****
--- 3100,3107 ----
*/
slot->seconds = time.tv_sec;
+ (u_char)ctrl_ws->reg_1 = (u_char)slot->cmd_ref;
+ #ifdef XCR_8BIT_REG
/*
* We have the controller
* Send cmd and id then the rest of the Registers
***************
*** 3079,3090 ****
--- 3154,3191 ----
* Make sure that this go out first
*/
WBFLUSH();
+ #else
+ /*
+ * We have the controller
+ * Send cmd and id then the rest of the Registers
+ */
+
+ tmp_ptr = (u_int *)&ctrl_ws->reg_0;
+
+ WRITE_BUS_D32(softc->sc_iohandle + XCR_MBX0, *tmp_ptr);
+ ++tmp_ptr;
+ WRITE_BUS_D32(softc->sc_iohandle + XCR_MBX4, *tmp_ptr);
+ ++tmp_ptr;
+ WRITE_BUS_D32(softc->sc_iohandle + XCR_MBX8, *tmp_ptr);
+ /*
+ * Do not do the last one on 32 bit boundary since this can
+ * overwrite status
+ */
+ if( ctrl_ws->xcr_val_regs & 0x1000){
+ WRITE_BUS_D8(softc->sc_iohandle + XCR_MBXC, (char)ctrl_ws->reg_c);
+ }
+ /*
+ * Make sure that this go out first
+ */
+ WBFLUSH();
+ #endif
/*
* Now indicate to the contoller to take the command
*/
WRITE_BUS_D8(softc->sc_iohandle + EISA_LDBELL, XCR_CMDIN);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + EISA_LDBELL);
/*
we can release sc lock before all these register writes but the
***************
*** 3161,3166 ****
--- 3262,3268 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, 0x08);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
/*
* Now we have tp wait up to 5 seconds for the bit to clear.
*/
***************
*** 3211,3216 ****
--- 3313,3319 ----
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
/*
* We are suppose to delay 75ms then wait for upto 2 minutes
***************
*** 3279,3284 ****
--- 3382,3388 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + 0x3F, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + 0x3F);
/*
* Check to see if controller is dead.
***************
*** 3301,3306 ****
--- 3405,3411 ----
if( result & XCR_DRV_SEQ ){
WRITE_BUS_D8(softc->sc_iohandle + 0x3F, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + 0x3F);
/*
* We must now wait for another 2 minutes..
*/
***************
*** 3347,3352 ****
--- 3452,3458 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
}
***************
*** 3355,3360 ****
--- 3461,3467 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + PCI_SYS_INTR, XCR_INTR_ENABLE);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_SYS_INTR);
XCR_UNLCK_REG(softc, spl );
***************
*** 3406,3411 ****
--- 3513,3519 ----
CNTRL_WS *cnt_ws; /* Pointer to the controller working
set */
CMD_QUE *slot; /* Pointer to the cmd que slot. */
int spl, spl1;
+ u_int tmp;
u_char id, status1, status2; /* our register that we read */
static u_char module[] = "xcrpintr";
***************
*** 3443,3451 ****
/*
* It interrupted us now get the registers we need...
*/
! id = READ_BUS_D8( softc->sc_iohandle + XCR_P_MBXD );
! status1 = READ_BUS_D8( softc->sc_iohandle + XCR_P_MBXE );
! status2 = READ_BUS_D8( softc->sc_iohandle + XCR_P_MBXF );
/*
* Now dismiss this interrupt
--- 3551,3566 ----
/*
* It interrupted us now get the registers we need...
*/
! /*
! id = READ_BUS_D8( softc->sc_iohandle + XCR_P_MBXD );
! status1 = READ_BUS_D8( softc->sc_iohandle + XCR_P_MBXE );
! status2 = READ_BUS_D8( softc->sc_iohandle + XCR_P_MBXF );
! */
!
! /*
! * Do the read on 32bit boundary
! */
! tmp = READ_BUS_D32( softc->sc_iohandle + XCR_P_MBXC );
/*
* Now dismiss this interrupt
***************
*** 3454,3463 ****
--- 3569,3590 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
XCR_UNLCK_REG(softc, spl);
/*
+ * Now get the results
+ * id is in bits 8 - 15
+ * status1 bits 16 - 23
+ * status2 bits 24 - 31
+ */
+ id = ((tmp >> 8) & 0xff);
+ status1 = ((tmp >> 16) & 0xff);
+ status2 = ((tmp >> 24) & 0xff);
+
+
+ /*
* Get the address of the command slot
* Make sure that it was active then clear the active bit
*/
***************
*** 3541,3546 ****
--- 3668,3674 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, 0x08);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
/*
* Now we have tp wait up to 5 seconds for the bit to clear.
*/
***************
*** 3592,3597 ****
--- 3720,3726 ----
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
/*
* We are suppose to delay 75ms then wait for upto 2 minutes
***************
*** 3654,3659 ****
--- 3783,3789 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + PCI_DBELL, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_DBELL);
/*
* Check to see if controller is dead.
***************
*** 3676,3681 ****
--- 3806,3812 ----
if( result & XCR_DRV_SEQ ){
WRITE_BUS_D8(softc->sc_iohandle + PCI_DBELL, result);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_DBELL);
/*
* We must now wait for another 2 minutes..
*/
***************
*** 3722,3727 ****
--- 3853,3859 ----
WBFLUSH();
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, XCR_STATUS_ACK);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
}
***************
*** 3730,3735 ****
--- 3862,3868 ----
*/
WRITE_BUS_D8(softc->sc_iohandle + PCI_SYS_INTR, XCR_INTR_ENABLE);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_SYS_INTR);
XCR_UNLCK_REG(softc, spl );
***************
*** 3773,3778 ****
--- 3906,3912 ----
{
XCR_SOFTC *softc = ctrl_ws->cntrl_softc;
int spl, spl1;
+ u_int *tmp_ptr = (u_int *)NULL;
int spin_cnt = 0;
static u_char module[] = "xcr_p_do_cmd";
***************
*** 3842,3851 ****
--- 3976,3988 ----
*/
slot->seconds = time.tv_sec;
+ (u_char)ctrl_ws->reg_1 = (u_char)slot->cmd_ref;
+
/*
* We have the controller
* Send cmd and id then the rest of the Registers
*/
+ #ifdef XCR_8BIT_REG
WRITE_BUS_D8(softc->sc_iohandle + XCR_P_MBX0, (char)ctrl_ws->reg_0);
WRITE_BUS_D8(softc->sc_iohandle + XCR_P_MBX1, (char)slot->cmd_ref);
***************
*** 3894,3905 ****
--- 4031,4066 ----
* Make sure that this go out first
*/
WBFLUSH();
+ #else
+ /*
+ * We have the controller
+ * Send cmd and id then the rest of the Registers
+ */
+ tmp_ptr = (u_int *)&ctrl_ws->reg_0;
+ WRITE_BUS_D32(softc->sc_iohandle + XCR_P_MBX0, *tmp_ptr);
+ ++tmp_ptr;
+ WRITE_BUS_D32(softc->sc_iohandle + XCR_P_MBX4, *tmp_ptr);
+ ++tmp_ptr;
+ WRITE_BUS_D32(softc->sc_iohandle + XCR_P_MBX8, *tmp_ptr);
+ /*
+ * Do not do the last one on 32 bit boundary since this can
+ * overwrite status
+ */
+ if( ctrl_ws->xcr_val_regs & 0x1000){
+ WRITE_BUS_D8(softc->sc_iohandle + XCR_P_MBXC, (char)ctrl_ws->reg_c);
+ }
+ /*
+ * Make sure that this go out first
+ */
+ WBFLUSH();
+ #endif
/*
* Now indicate to the contoller to take the command
*/
WRITE_BUS_D8(softc->sc_iohandle + PCI_LDBELL, XCR_CMDIN);
WBFLUSH();
+ (void)READ_BUS_D8(softc->sc_iohandle + PCI_LDBELL);
/*
we can release sc lock before all these register writes but the
***************
*** 3912,3915 ****
--- 4073,4078 ----
return;
}
+
+
Output from "diff xcr_port.c xcr_port.c.orig > & diff.log"
-----------------------------------------------------------
7,11d6
< * Revision 1.1.35.2 1995/12/04 18:56:03 John_Steinman
< * Back port of fix for DMO100161 (QAR #39130). Don't panic insert special
< * command at tail of pending queue when there's no regular I/O and a
special
< * command(s) already on the queue. - authored by Cheryl_Deleo
< *
18c13
< *
---
> *
23c18
< *
---
> *
82c77
< #pragma ident "@(#)$RCSfile: xcr_port.c,v $ $Revision: 1.1.35.2 $ (DEC)
$Date: 1995/12/04 18:56:03 $"
---
> #pragma ident "@(#)$RCSfile: xcr_port.c,v $ $Revision: 1.1.26.2 $ (DEC)
$Date: 1995/07/19 19:35:34 $"
1226,1231c1221
< }
< /*
< * If we didn't find any regular I/O on the queue just
< * insert the "special" command at the tail of the queue
< * (ie. after the other special command(s))...Don't panic
< */
---
> }
1233c1223
< XCR_INSERT_PND( xcr_softc, cnt_ws);
---
> panic("xcr_que_insert list corruption");
*******************************************************************************
John F. Steinman
USEG (UNIX(R) Support Engineering Group) Phone: (603) 881-0502
Enet: guru::steinman DTN: 381-0502
Internet: [email protected] Mailstop: ZK03-2/T43
*******************************************************************************
| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 1972.1 | Re: U/A: v32supportos-193-steinman bdiff and diff does not match | AOSG::FILTER | Automatic Posting Software - mail to flume::puck | Mon Dec 04 1995 20:27 | 30 |
| Date Of Receipt: 4-DEC-1995 14:29:47.36
From: SMURF::FLUME::johnf "John Flanagan USG Test Johnf Tools Group 04-Dec-1995 1425"
To: John Steinman - USEG DTN381-0502 <[email protected]>
CC: [email protected], [email protected], [email protected],
[email protected], [email protected]
Subj: Re: U/A: v32supportos-193-steinman bdiff and diff does not match
What are you backed by?
bdiff -r$NEW gets you the LATEST version out of the SUBMIT tree.
bco gets you the latest version out of the backingtree you are backed by.
There can be a difference.
John
______________________________________________________________________
John Flanagan enet: [email protected]
MS: ZKO3-3/W20 decnet: flume::johnf
USG Release Engineering (603) 881-1719
110 Spitbrook Road (DTN) 381-1719
Nashua, NH
______________________________________________________________________
|
| 1972.2 | Re: U/A: v32supportos-193-steinman bdiff and diff does not match | AOSG::FILTER | Automatic Posting Software - mail to flume::puck | Mon Dec 04 1995 20:28 | 23 |
| Date Of Receipt: 4-DEC-1995 14:37:56.63
From: SMURF::WASTED::"[email protected]" "04-Dec-1995 1433"
To: John Flanagan - UNIX Systems Group <[email protected]>
CC: John Steinman - USEG DTN381-0502 <[email protected]>,
[email protected], [email protected],
[email protected], [email protected],
[email protected]
Subj: Re: U/A: v32supportos-193-steinman bdiff and diff does not match
csh> currentsb -all
v32_dmo100161 John_Steinman_v32_dmo100161 /usr/sandboxes/steinman/sandboxes .
/usr/sandboxes/steinman/sandboxes/v32_dmo100161/rc_files/local
/share/secret/build/submits.dsk2/v32supportos
I get the same result between bdiff and diff if a back to v32supportos.nightly.
*******************************************************************************
John F. Steinman
USEG (UNIX(R) Support Engineering Group) Phone: (603) 881-0502
Enet: guru::steinman DTN: 381-0502
Internet: [email protected] Mailstop: ZK03-2/T43
*******************************************************************************
|
| 1972.3 | Re: U/A: v32supportos-193-steinman bdiff and diff does not match | AOSG::FILTER | Automatic Posting Software - mail to flume::puck | Mon Dec 04 1995 20:32 | 28 |
| Date Of Receipt: 4-DEC-1995 15:03:19.44
From: SMURF::FLUME::johnf "John Flanagan USG Test Johnf Tools Group 04-Dec-1995 1456"
To: John Steinman - USEG DTN381-0502 <[email protected]>
CC: John Flanagan - UNIX Systems Group <[email protected]>,
[email protected], [email protected],
[email protected], [email protected],
[email protected]
Subj: Re: U/A: v32supportos-193-steinman bdiff and diff does not match
Upon closer investigation, the variable "NEW" was being set incorrectly
in the v32supportos tree. This has been fixed, and John's bdiff now produces
the proper results.
John
______________________________________________________________________
John Flanagan enet: [email protected]
MS: ZKO3-3/W20 decnet: flume::johnf
USG Release Engineering (603) 881-1719
110 Spitbrook Road (DTN) 381-1719
Nashua, NH
______________________________________________________________________
|