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<P>
The LM_ENC contains *TBD* 16-bit control and status registers addressed from *TBD* to *TBD*.
Each individual register is presented in detail in the following sections.
<ALIGN_CHAR>(#)
<P>
The Physical Connection Management Control Register (PCM_CNTRL) contains
signals and requests to the PCM.
<TABLE>(PCM_CNTRL -- Physical Connection Management Control Register\PCM_CNTRL)
<TABLE_ATTRIBUTES>(\MULTIPAGE)
<TABLE_SETUP>(3\4\6)
<FOOTNOTE>(1\All bits of this register are read/write)
<TABLE_HEADS>(#BIT\NAME\DEFINITION<FOOTREF>(1))
<TABLE_ROW>(15:12\##-\##-\Undefined)
<TABLE_ROW>(11:09\PCM_Maint_LS\The PCM_Maint_LS defines the line state
the PCM will source while in the MAINTENANCE state. The PCM enters the
MAINTENANCE state from the OFF state in response to the assertion of the
PCMCTL pin. It is further defined as follows:)
<TABLE_ROW>(\\
<TABLE>
<TABLE_SETUP>(2\10)
<TABLE_HEADS>(PCM_Maint_LS Value\Description)
<TABLE_ROW>(000\Transmit_QUIET line state)
<TABLE_ROW>(001\Transmit_IDLE line state)
<TABLE_ROW>(010\Transmit_HALT line state)
<TABLE_ROW>(011\Transmit_MASTER line state)
<TABLE_ROW>(100\Transmit_JK line state)
<TABLE_ROW>(101\Transmit_PDR (Transmit PHY_DATA.request) -- the symbol
stream coming in on TXDATA(9:0) is transmitted.)
<TABLE_ROW>(110-111\Undefined)
<ENDTABLE>)
<TABLE_ROW>(\\This field is written by the node processor and unchanged
by the PCM. With the assertion of PWRESL the PCM_Maint_LS parameter is set
to transmit_QUIET.)
<TABLE_ROW>(##08\PCM_Stop\When set this bit causes the PCM to transition
to the OFF state from whatever state it should happen to be in. PCM_Stop is
cleared by the assertion of PWRESL and unchanged by the PCM.)
<TABLE_ROW>(07:04\##-\##-\Undefined)
<TABLE_ROW>(03:01\PCM_Class\The PCM_Class parameter
defines the type of attachment for the physical link controlled by
this PCM. It is further defined as follows:)
<TABLE_ROW>(\\
<TABLE>
<TABLE_SETUP>(3\7\5)
<TABLE_HEADS>(PCM_Class Value\Mnemonic\Description)
<TABLE_ROW>(000\M\Master)
<TABLE_ROW>(001\M'\Wiring Concentrator special Master)
<TABLE_ROW>(010\S\Slave)
<TABLE_ROW>(011\S'\Wiring Concentrator special Slave)
<TABLE_ROW>(100-110\Undefined)
<TABLE_ROW>(111\Null)
<ENDTABLE>)
<TABLE_ROW>(\\This field is written by the node processor and unchanged
by the PCM. With the assertion of PWRESL the PCM_Class parameter is set to
NULL.)
<TABLE_ROW>(##00\PCM_Start\When set this bit causes the PCM to transition
from OFF to BREAK. Note, however, if the PCM_Class field has not been changed
from NULL or is undefined, or the PCM_Stop bit is set,
the PCM remains in the OFF state. The PCM_Stop, PCM_Class and PCM_Start bit
may be written in a single write access and, given each is written with
something valid, the PCM will make the OFF to BREAK transition.
PCM_Start is cleared by the PCM when it enters the BREAK state
and with the assertion of INT_RES_L.)
<ENDTABLE>
<P>
The Physical Connection Management Control Register (PCM_STATUS) contains
signals and status from the PCM.
<TABLE>(PCM_STATUS -- Physical Connection Management Status Register\PCM_STATUS)
<TABLE_ATTRIBUTES>(\MULTIPAGE)
<TABLE_SETUP>(3\4\6)
<FOOTNOTE>(1\All bits of this register are read-only)
<FOOTNOTE>(2\The assertion of PCM_Stop has the same effect on the bits of this
register as does INT_RES_L)
<TABLE_HEADS>(#BIT\NAME\DEFINITION<FOOTREF>(1)<FOOTREF>(2))
<TABLE_ROW>(##08\PCM_Active\When set this bit indicates the PCM at the
remote station has passed the test phase of the connection process and
this PCM has transitioned to the ACTIVE state.
PCM_Active is cleared with the assertion of INT_RES_L. Once set, PCM_Active
is cleared only when the PCM exits the ACTIVE state.)
<TABLE_ROW>(##07\PCM_Enabled\When set this bit indicates the PCM has
passed the TEST phase of the connection process and is in ENABLE state.
PCM_Enabled is cleared with the assertion of INT_RES_L. Once set, PCM_Enabled
is cleared only when the PCM exits the ENABLE state.)
<TABLE_ROW>(##06\PCM_Disabled\When set this bit indicates the PCM has
disabled a connection it has previously accepted (PCM_Mode set). PCM_Disabled is
cleared with the assertion of INT_RES_L. Once set, PCM_Disabled is cleared
when PCM_Mode is once again ascertained.)
<TABLE_ROW>(##05\PCM_Waiting\When set this bit indicates the PCM has been stuck
in the DISABLE state for a time greater than twice TD_React without detecting
a valid exit condition from DISABLE. PCM_Waiting is cleared with the assertion of
INT_RES_L. Once set, the bit is only cleared when the PCM exits the DISABLE
state.)
<TABLE_ROW>(##04\PCM_Broken\When set this bit indicates the PCM has been stuck
in the BREAK state for a time greater than twice TB without detecting a valid
exit condition from BREAK. PCM_Broken is cleared with the assertion of INT_RES_L.
Once set, the bit is only cleared when the PCM exits the BREAK state.)
<TABLE_ROW>(##03\PCM_Off\When set this bit indicates the PCM has transitioned
to the OFF state. PCM_Off is set with the assertion of INT_RES_L.)
<TABLE_ROW>(02:00\PCM_Mode\The PCM_Mode parameter indicates the mode of
physical connection the PCM has detected when in the DISABLE state.
It is further defined as follows:)
<TABLE_ROW>(\\
<TABLE>
<TABLE_SETUP>(3\7\5)
<TABLE_HEADS>(PCM_Mode Value\Mnemonic\Description)
<TABLE_ROW>(000\NULL\No Connection has been established.)
<TABLE_ROW>(001\F\Full Duplex connection (Slave-to-Slave).)
<TABLE_ROW>(010\MS\Master-Slave connection.)
<TABLE_ROW>(011\MS'\Master-WC special Slave connection.)
<TABLE_ROW>(100\M'S'\WC special Master-WC special Slave connection.)
<TABLE_ROW>(101-111\-\Undefined)
<ENDTABLE>)
<TABLE_ROW>(\\With the assertion of INT_RES_L the PCM_Mode parameter is set to
NULL. Also, PCM_Mode is set to NULL when the physical connection is disabled
by the PCM (PCM_Disabled asserted).)
<ENDTABLE>
<P>
The PCM contains two timers for general use while establishing a
physical connection. Each timer is 24 bits wide and is read-only by the
node processor.
<P>
The Line Activity Timer (TLA) is used by the PCM to time how long it
has been in a particular state. The Line State Timer (TLS) is used by
the PCM to time how long a particular line state is being reported by
the LSM. See section ... put timer ref here ... for more information
on the use of TLA and TLS.
<ENDALIGN_CHAR>
<P>
The LM_ENC contains four counters for the purpose of gathering statistics
about its associated physical link. Each counter is eight bits, has
its own address, and is read-only by the node processor interface.
The upper eight bits of each counter will be read as zeroes.
Interrupts may be generated when
any of the counters increments or overflows, depending on whether or not
the associated interrupt has been enabled in the IEMR.
<P>
The VIOLATION CounTeR (VIOLATION_CTR) keeps track of the number of times a
violation has been
reported to the LM_ENC from the Elasticity Buffer (E_BUFF). The E_BUFF
signals a VIOLATION whenever its internal buffer overflows or underflows.
<P>
The LOSS of Signal Detect CounTeR (LOSS_SD_CTR) is incremented with the
deassertion of the Signal Detect (SD)
pin. See section ... put ref here ... for more information on the SD pin.
<P>
The PHYsical Layre INValid CounTeR (PHYINV_CTR) counts the number of times the
physical link has been disabled
by the physical connection management state machine (PCM). PHYINV_CTR is
incremented whenever the PCM transitions from ACTIVE to BREAK or ACTIVE to
DISABLE.
<P>
The VIOLation SYMbol CounTeR (VIOL_SYM_CTR) is incremented each time the
4B/5B decoder in the LM_ENC decodes a violation symbol.
<P>
The LM_ENC contains one 16-bit, read-only, register that contains the
resultant signature after execution of the chips selftest. After BiST
has been completed, this register should be read and its contents compared
against the known good signature for the LM_ENC to determine whether the
chip has passed its selftest.
<ALIGN_CHAR>(#)
<P>
The Interrupt Event Register is used by the LM_ENC to report events to the node
processor. When an interrupt is generated (through LM_INT_L), the node
processor should read this register to find out the source of the interrupt.
<TABLE>(Interrupt Event Register (IER)\IER)
<TABLE_SETUP>(3\5\12)
<FOOTNOTE>(1\All bits of this register are cleared with the assertion of
INT_RES. They are set individually by the LM_ENC for the particular event
occurances. All bits are cleared when the node processor reads this register.)
<TABLE_HEADS>(BIT\NAME\DEFINITION<FOOTREF>(1))
<TABLE_ROW>(14:09\##-\Undefined)
<TABLE_ROW>(##07\NP_ERR\The Node Processor has requested a read or write to
an invalid register. This case includes a write to a read-only register
(such as this one).)
<TABLE_ROW>(##14\LSM_ST_CHNG\An event indicating a state change in the LSM.)
<TABLE_ROW>(##13\VSYM_CTR_OVF\An event indicating the violation symbol counter has overflowed.)
<TABLE_ROW>(##12\PINV_CTR_INC\An event indicating the physical layer invalid counter has been
incremented.)
<TABLE_ROW>(##11\PINV_CTR_OVF\An event indicating the physical layer invalid counter has
overflowed.)
<TABLE_ROW>(##10\VIOL_CNTR_INC\An event indicating the violation counter has been incremented.)
<TABLE_ROW>(##09\VIOL_CNTR_OVF\An event indicating the violation counter has overflowed.)
<TABLE_ROW>(##08\LSD_CNTR_INC\An event indicating the Loss of signal detect counter has
been incremented.)
<TABLE_ROW>(##07\LSD_CNTR_OVF\An event indicating the Loss of signal detect counter has overflowed.)
<TABLE_ROW>(##06\PCM_Active\An event indicating the start of the PCM_Active
condition.)
<TABLE_ROW>(##05\PCM_Enabled\An event indicating the start of the PCM_Enabled
condition.)
<TABLE_ROW>(##04\PCM_Disabled\An event indicating the start of the PCM_Disabled
condition.)
<TABLE_ROW>(##03\PCM_Waiting\An event indicating the start of the PCM_Waiting
condition.)
<TABLE_ROW>(##02\PCM_Broken\An event indicating the start of the PCM_Broken
condition.)
<TABLE_ROW>(##01\PCM_Off\An event indicating the start of the PCM_Off
condition.)
<TABLE_ROW>(##00\BiST_DONE\An event indicating the LM_ENC's BiST has
completed. Note, during the execution of BiST all other interrupts to the
node processor are blocked except BiST_DONE. However, when reading this
register after the BiST_DONE interrupt, other bits may be set.)
<ENDTABLE>
<ENDALIGN_CHAR>
<P>
The interrupt event mask register allows the disabling of interrupts caused
by specific events. The IEMR contains a bit that corresponds with each bit
of the IER that, when clear, prohibits that condition from causing an
interrupt to the node processor. For each set bit, the setting of the
corresponding bit in the IER will generate an interrupt to the node processor
via the LM_INT_L pin of the LM_ENC. All bits of the IEMR are cleared with the
assertion of INT_RES. They may be set or cleared by the node processor and are
unchanged by the LM_ENC.
<P>
The rest of the control and status information for the LM_ENC is contained
in two registers.
<P>
The LM_ENC Control register (LM_ENC_CNTRL) is the means by which the following
functions are carried out:
<LIST>(UNNUMBERED)
<LE>LM_ENC Data path configuration
<LE>Execute Chip Selftest
<LE>Reset Chip to known state, and
<LE>Communicate functions to lower PHY and PMD entities
<ENDLIST>
<ALIGN_CHAR>(#)
<TABLE>(LM_ENC_CNTRL -- LM_ENC Control Register\LM_CNTRL)
<TABLE_ATTRIBUTES>(\MULTIPAGE)
<TABLE_SETUP>(3\5\12)
<FOOTNOTE>(1\All bits of this register are read/write)
<TABLE_HEADS>(#BIT\NAME\DEFINITION<FOOTREF>(1))
<TABLE_ROW>(15:09\##--\Undefined)
<TABLE_ROW>(##08\CSR_RESL\This bit, asserted low, is OR'ed together with
PWRESL to create the INT_RES_L signal. INT_RES_L will reset all the
LM_ENC's state machines. The effect of INT_RES_L upon the node processor
registers is called out explicitly in their definitions.)
<TABLE_ROW>(##07\FOTOFF\When set causes the FOTOFF output pin to be asserted
which will cause the fiber optic transmitter to turn
OFF (via the CDCT chip). With the assertion of INT_RES_L, the FOTOFF
bit is cleared.)
<TABLE_ROW>(##06\CDC_LOOP_CNTRL\When set causes the CDCLPC output pin to be
asserted. This, in turn, causes data to be looped back
from the output of the CDCT chip to the input of the
CDCR chip. The bit resides in the LM_ENC because the CDCR chip does not
contain any CSRs. With the assertion of INT_RES_L, CDC_LOOP_CNTRL is cleared.)
<TABLE_ROW>(##05\LM_LOC_LOOP\When set a local loopback path is set up in the
LM_ENC chip just prior to the LM_ENC-to-E_BUF interface. Data from
TX_DATA(9:0) is passed through the LM_ENC transmit path and looped back onto
the receive path at RC_MUX1. LM_LOC_LOOP only takes effect if the PCM is
in OFF or MAINTENANCE, otherwise, it is ignored. With the assertion of
INT_RES_L, LM_LOC_LOOP is cleared.)
<TABLE_ROW>(##04\SC_REM_LOOP\When set a remote loopback path is set up
inside the LM_ENC where symbols from the receive data path are
looped back onto the transmit data path at the output of the DECODER through
TX_MUX2. SC_REM_LOOP and LM_LOC_LOOP should not be set at the same time as this
will create a loop within the LM_ENC.)
<TABLE_ROW>(##03\SC_BYPASS\When set, SC_BYPASS causes the physical link
controlled by the LM_ENC to be bypassed. This is done by switching RC_MUX2
to route the byte stream from TXDAT(9:0) on to RCDAT(9:0).
This bit is used by the wiring concentrator for the insertion and removal
of a station from the ring. SC_BYPASS is set with the assertion of INT_RES_L.)
<TABLE_ROW>(##02\RF_ENABLE\When set this bit enables the repeat filter
function of the LM_ENC. RF_ENABLE is cleared with the assertion of INT_RES_L.)
<TABLE_ROW>(##01\EBUF_TESTI\ ... DEFINE THIS ...)
<TABLE_ROW>(##00\RUN_BiST\When set, RUN_BiST causes the LM_ENC to begin
running its Built-in SelfTest. The completion of BiST is indicated through
the BiST_DONE interrupt in the interrupt event register. RUN_BiST is cleared
with the assertion of INT_RES_L.)
<ENDTABLE>
<P>
The LM_ENC Status register (LM_ENC_STATUS) is the means by which status
information is reported to the node processor. Note the PCM status is
in a separate register.
<TABLE>(LM_ENC_STATUS -- LM_ENC Status Register\LM_STAT)
<TABLE_SETUP>(3\5\8)
<FOOTNOTE>(1\All bits of this register are read-only)
<TABLE_HEADS>(#BIT\NAME\DEFINITION<FOOTREF>(1))
<TABLE_ROW>(15:09\##--\Undefined)
<TABLE_ROW>(06:04\LSM_PSP\This field contains the previous symbol pair
recognized by the Line States State Machine (LSM). It is further defined
as follows:)
<TABLE_ROW>(\\ ... PUT PSP STUFF HERE ... )
<TABLE_ROW>(03:01\LSM_CLS\This field contains the most recently
recognized line state by the LSM. LSM_CLS is further defined as
follows:)
<TABLE_ROW>(\\ ... PUT CLS STUFF HERE ... )
<TABLE_ROW>(\\The field is cleared (QUIET line state) with the assertion of
INT_RES_L.)
<TABLE_ROW>(##00\LSM_ULSB\This bit is the Unkown Line State Bit from the
LSM. Since a minimum of 16 symbols is required to satisfy the
entry conditions of a line state, the LSM uses this bit to indicate it
is attempting to recognize a new line state.)
<ENDTABLE>
<ENDALIGN_CHAR>
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