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| Title: | VAX on VMEbus: KAV30 |
| Notice: | Could have been as fast as 68K but its a VAX! |
| Moderator: | CSSVMS::KAV30_SUPP |
|
| Created: | Thu Apr 18 1991 |
| Last Modified: | Fri Aug 02 1996 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 159 |
| Total number of notes: | 645 |
13.0. "CDB 8210 CAMAC Branch Driver Library in Fieldtest" by ZURFCC::SEITZ (Matthias Seitz, Swiss Design Win Team, THR 3367) Wed May 15 1991 12:10
CDB 8210 CAMAC Branch Driver VAXELN Library is in Fieldtest now
---------------------------------------------------------------
The Software is written by Digital Switzerland (Christian Mischler)
whithin a joint development project with the Paul Scherrer Institute
of the Swiss Federal Institute of Technology (ETH).
Legal Considerations:
The CAMAC Driver Software Library is proprietary to
Digital and may be unrestrictedly distributed by
Digital, with the following exeption:
The CAMAC Driver Software Library and Source code may
be unlimitedly used by all Institutions of the Swiss
Federal Institute of Technology (ETH). (In German: Alle
Eidgenoessischen Hochschulen, Institute und
Einrichtungen, die der Aufsticht des Schweizerischern
Schulrats unterstehen).
The following CAMAC Library routines have been implemented.
CDREG combines the branch number, crate number, station
number and the subaddress into a longword which can be
used to access a specific address within the CAMAC.
CFSA causes the CAMAC action specified by the function_code
to be performed at a specific CAMAC address. 24 bit
data is read or written.
CSSA causes the CAMAC action specified by the function_code
to be performed at a specific CAMAC address. 16 bit
data is read or written.
CCCZ causes Dataway Initialize (Z) to be generated in the
crate specified by the external address.
CCCC causes Dataway Clear (C) to be generated in the crate
specified by the external address.
CCCI causes Dataway Inhibit (I) to be set or cleared in the
crate specified by external address.
CTCI tests whether the Dataway Inhibit is set or cleared
within the crate specified by external address.
CCCD causes Crate Demand to be enabled or disabled in the
crate specified by external address.
CTCD tests whether the Crate Demand is enabled or disabled in
the crate specified by external address.
CTGL tests whether a Crate Demand is present in the crate
specified by external address.
CFGA causes a sequence of CAMAC functions specified in
successive elements of function_code_array to be
performed at a corresponding sequence of CAMAC
addresses specified in successive elements of
external_address_array. For each function there is a
corresponding 24 bit data to be written or read in
long_data_array. The number of functions to perform is
stored within the first element of control_block.
CSGA causes a sequence of CAMAC functions specified in
successive elements of function_code_array to be
performed at a corresponding sequence of CAMAC
addresses specified in successive elements of
external_address_array. For each function there is a
corresponding 16 bit data to be written or read in
long_data_array. The number of functions to perform is
stored within the first element of control_block.
CFUBC causes the single CAMAC function given by the value of
function_code to be executed at the CAMAC address
specified by the value of external_address. During the
"block transfer" the CAMAC address is never changed,
but the single register is expected to supply or accept
many words of data. The transfer can be terminated by
the module or by this procedure. This procedure
terminates the transfer when the number of transfers
which are specified within the first element of
control_block are performed. The module terminates the
transfer when there are no more data to be accepted or
written. The module signals this with a Q response of 0
(FALSE). There are two stop modes supported by module.
An UCS (stop mode) module will generate Q = 0 after the
first data not readable or writeable has been is
transferred. An UCW (stop on word mode) module will
generate Q = 0 after the last data readable or
writeable has been transferred.
CSUBC causes the single CAMAC function given by the value of
function_code to be executed at the CAMAC address
specified by the value of external_address. During the
"block transfer" the CAMAC address is never changed,
but the single register is expected to supply or accept
many word of data. The transfer can be terminated by
the module or by this procedure. This procedure
terminates the transfer when the number of transfers
which are specified within the first element of
control_block are performed. The module terminates the
transfer when there are no more data to be accepted or
written. The module signals this with a Q response of 0
(FALSE). There are two stop modes supported by module.
An UCS (stop mode) module will generate Q = 0 after the
first data not readable or writeable has been is
transferred. An UCW (stop on word mode) module will
generate Q = 0 after the last data readable or
writeable has been transferred.
CDLAM encodes the branch number, the crate number, the
station number, the station subaddress and the number
of the associated GLAM into a 32 bit longword.
CCLM causes the LAM specified by the lam_identifier to be
enabled or disabled.
CCLC causes the LAM specified by lam_identifier to be
cleared.
CTLM tests whether the LAM specified by lam_identifier is
asserted or deasserted.
CCLNK links a standard interrupt service routine to the
specified LAM (GLAM). The interrupt service routine
does nothing but signaling the device object when the
LAM occurs. The calling process then can wait for this
object. Optionally a process can be created by
specifying int_service_process.
Note: This routine would be used if the data arrives at
a low frequency and there are a lot of actions to be
performed after each interrupt.
CCLNK_ISR links a specific interrupt service
(int_service_routine) routine to the specified LAM
(GLAM). As example the interrupt service routine could
read some data at a high frequency into a buffer and
the signal the device object to let a process read the
buffer at once.
Note: This routine would be used if the data arrives at
a high frequency and there are only a few actions to be
performed after each interrupt. As example buffering.
At the Moment we are optimizing these routines in terms of
ISR Latency and Response Time.
Then we are doing some benchmarks which will be published as replies
to this note.
Matthias Seitz / Tech Advisory and Project Leader
| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 13.1 | Architectural question: why not RT300 in Camac? | CESARE::OLOBARDI | Marco - CSO Mktg Italy - P&P OEM | Thu May 23 1991 20:29 | 12 |
| Matthias,
could you please explain briefly the Architectural concept?
I would imagine a KAV30 in a VME crate with a VME board acting as
Camac branch driver connected to one or several Camac crates.
Wouldn't be the same (at lower cost, possibly) having several
Camac crates with the "RT300-based board from Kinetics" (can't
remember the name) sitting right into the camac crate?
Ciao and thanks in advance.
Marco
|
| 13.2 | This is the real acquisition architecture | ZURFCC::SEITZ | Matthias Seitz, Swiss Design Win Team, THR 3367 | Thu Jun 13 1991 11:18 | 28 |
|
Yes you may be right in general. But the architectture is built around the VME
bus to expand the measuring system with other acquisition modules e.g.
Fastbus or others.
+-------------------+
| VMS VAX 9000 |
+-------------------+
| Ethernet
=--------------------------------------------------=
|
+-----------------+
| KAV30 |
+-----------------+
| VMEbus
============================================================
| |
+---------------------+ +---------------------------+
| Camac Branch Driver | | OTHER VMEbus |
| CBD 82100 | | Data Acquisition Devices |
+---------------------+ | e.g Fastbus ... |
| +---------------------------+
v
To CAMAC Devices
regards Matthias
|