[Search for users] [Overall Top Noters] [List of all Conferences] [Download this site]

Conference 49.910::kav30

Title:VAX on VMEbus: KAV30
Notice:Could have been as fast as 68K but its a VAX!
Moderator:CSSVMS::KAV30_SUPP
Created:Thu Apr 18 1991
Last Modified:Fri Aug 02 1996
Last Successful Update:Fri Jun 06 1997
Number of topics:159
Total number of notes:645

7.0. "Performance" by EICMFG::NORDH (EIS/Engineering Munich, DTN 773-3142) Thu Apr 18 1991 12:44

T.RTitleUserPersonal
Name
DateLines
7.1performace summaryGOBANG::LEMMERFri Dec 06 1991 18:4348

	This paper presents a summary of the KAV30 performance data.
	The complete performance report is published with the release
	notes for the KAV30 toolkit version 1.1.


	programmed I/O (write) �)	max.		2.7 Mbyte/sec

	programmed I/O (read)  �)	max.		1.6 Mbyte/sec

	DMA I/O peak	       �)	max.		5   Mbyte/sec

	DMA I/O typical	       �)			2.5 Mbyte/sec

	context switch preempt �)	min.		112�sec

	context switch wait    �)	min.		140�sec

	interrupt latency      �)	min.		12 �sec


	�) Programmed I/O was measured with the system services
	   KAV$BUS_WRITE and KAV$BUS_READ and a size of 262144
	   longwords which is 1Mbyte. No network was connected, the
	   system clock was on and the job priority 0. Programmed I/O
	   without using the system service is about 15% slower (for 
	   a transfer size of several kbytes and above - programmed
	   I/O to single words/longwords (registers) on the VMEbus
	   is fastest without the system service). The timer resolution 
	   was 1msec.

	�) The KAV30 cannot generate a DMA transfer, but can accept
	   DMA block transfer's up to 4 longwords from a DMA controller
	   on the VMEbus. One longword transfer needs 600nsec, this gives
	   the 5 Mbyte peak. A typical measurement was done with a FIC8230
	   CPU/DMA controller, this gave the result of 2.5 Mbytes/sec.
	   A faster DMA controller would probably result in a typical 
	   transfer rate of more than 4 Mbytes/sec.

	�) Context switching times were measured using the methods described
	   in the ELN release notes appendix A. There was no network and
	   no system clock and the job was running at priority 0. The
	   timer resolution was set to 2�sec.

	�) Interrupt latency is defined as the time from the interrupt-
	   assertion on the VMEbus to the first instruction within ISR,
	   it was measured using a logic analyzer.
7.2correctionGOBANG::LEMMERMon Dec 09 1991 09:328
	The previous entry contains an error:

	The 'cycle time' for block mode access is 600nsec for one longword,
	this is 150nsec for a byte and therefor the 'peak' DMA transfer
	is at 6.6 Mbytes per second and not at 5 Mbytes/sec.

	Thomas