Conference noted::corporate_cad_tool_directory

115.0. "Call for Papers - VHDL Design Process Forum (2)" by DIKYJR::WHITE () Mon Jan 13 1992 16:19

 **CALL FOR PAPERS**CALL FOR PAPERS**CALL FOR PAPERS**CALL FOR PAPERS**


			  ** CALL FOR PAPERS **

		       VHDL Design Process Forum (2)
		

		   March 25-26, 1992  MRO4 Amphitheater
	
A two day technical forum for all interested internal people.

This forum sponsored by USS ECAD, is dedicated to providing 
industry leaders in VHDL tool development and our own internal 
experts a medium to present products and experiences with VHDL.

_____________________________________________________________________


1. Proposed title of paper:__________________________________________


2. Presenter:
 
	   Name:__________________________________
	   Address:_______________________________
	   Phone:_________________________________
	   E-net Address:_________________________
	   Group:_________________________________
 	   Organization:__________________________
	   Presentation Time:_____________________

_______________________________________________________________________

3. Major Category:

We are particularly interested in receiving papers on direct experiences,
methods, ideas, and tools related to the following categories, although,
submissions are not limited to these categories.  

Please check one.

___VHDL and the CAD design process
___VHDL model libraries
___VHDL and simulation
___VHDL and logic synthesis

___Other (Please Specify)__________________



When writing your paper, please consider the following topics 
that were requested during the call for interest:

* uniform coding standards
* simulation performance modeling
* backannotation with VHDL
* VHDL simulation acceleration
* code management
* revision control
* standards updates
* simulation speed of VHDL models
* mixed language behavioral simulation
* latch/flop interfacing
* abstract data type support
* export to PLD/FPGA
* configuration support
* core simulation capabilities
* linkages to other tools such as frontend schematic, synthesis,
  physical layout tools etc.
* current status of VHDL tools internally
* silicon vendor support for VHDL
* ASIC libraries
* commercial chip models
* potential upgrades in IEEE 1076 standard
* debugging tools for VHDL

___________________________________________________________________________

4. Is this tool/service/product available NOW?

___Yes
___No

___________________________________________________________________________

5.  Technical Roundtables

If time permits, do you wish to sponsor a technical roundtable? 
(A small group discussion on a specific subject)

___Yes
___No

_______________________________________________________________________

6. Submittal Process

Draft abstracts should be one paragraph that clearly describe the
the intent of the paper. You have the option of submitting up 
to a four-page paper.  Enough detail must be given so reviewers can 
make a clear decision on the acceptance and placement of the paper.

Draft abstracts will be excepted in ASCII format but the final paper
must be in PostScript to be included in the proceedings. Be sure to include:
Author(s), Group, Location, DTN, Mailstop, E-net address, and a brief
biographical sketch of the author(s).

_______________________________________________________________________

7. Presentation Information

   Please include a short description suitable for use in the conference 
   program.



8. Have you previously conducted this or a similar presentation?

_____Yes                    _____No


9. What special requirements will you have as to audio-visual materials?



________________________________________________________________________

10. Conference Information:

	Abstract deadline:  January 24, 1992
	Notice of selection: February 3, 1992
	Final paper due: March 2, 1992
	Conference presentation: March 24/March 25, 1992



11. Send abstracts to:  Cheryl White, ML05-2/T40, DIKYJR::WHITE