Conference noted::corporate_cad_tool_directory

113.0. "Call for Topics - VHDL Forum (2)" by DIKYJR::WHITE () Mon Jan 06 1992 10:40

On July 25, 1991 the USS ECAD group hosted a VHDL Design Process Forum.  The 
response and feedback from Digital's engineering community were overwhelming 
positive.  

Because of our desire to meet your needs, we are considering a second VHDL 
Design Process Forum in March.  We hope to combine the industry leaders in VHDL 
tool development and expertise with those of us within Digital who have 
internal products to offer, or have a VHDL process or portion of a process 
in place today.

At this time we would like to encourage anyone who has a vested interest
in VHDL and VHDL based libraries/CAD tools to take part.  We are compiling
a list of TOPICS OF INTEREST before sending out a "Call for Papers".  
What topics would YOU like to learn more about?  Be as specific as possible
with titles of topics and please respond to this message by January 10.  A
"Call for Papers" will be going out on January 13.

Topics can relate to things like:

* uniform coding standards
* simulation performance modeling
* backannotation with VHDL
* VHDL simulation acceleration
* code management
* revision control
* standards updates
* simulation speed of VHDL models
* mixed language behavioral simulation
* latch/flop interfacing
* abstract data type support
* export to PLD/FPGA
* configuration support