Conference noted::corporate_cad_tool_directory

111.0. "VHDL Course" by MILRAT::CORADMIN () Thu Aug 29 1991 12:42

                  USS/Maynard Area Engineering Training
                  		& E.C.A.D.
--------------------------------------------------------------------------------
Title             VHDL                                                        
________________________________________________________________________________
Instructor        Dinesh Bettadapur, CLSI       
Date              18-SEP-91 - 20-SEP-91
Time              8:30 -  5:00
Location          William Knight Lab Rm MLO4-5  
Course Number     21CAD-01
Course Fee        $  995

Instructor	  Paul Menchini, CLSI
Date		  23-SEP-91 - 25-SEP-91
Time              8:30 -  5:00
Location          William Knight Lab Rm MLO4-5  
Course Number     21CAD-02
Course Fee        $  995


Registration      $SET HOST MILRAT
		  Username: COURSES
		  Password: TRAINING

Cancellation      WITHDRAWAL MUST OCCUR NO LATER THAN 11 WORK DAYS PRIOR TO   
                  CLASS START TO AVOID BEING CHARGED THE FULL COURSE FEE!!    

Description       VHDL is a hardware description language that is capable
                  of describing hardware from the gate level to the entire
                  system.  This language is a broad language which allows
                  modeling of existing components and design of new
                  components.
                                                                                
                  In addition, VHDL 1076 is the only standard HDL in
                  existence and has been adopted by all major EDA vendors.
                  This is due to the fact that the syntax and semantics of
                  the language are independently defined of any particular
                  simulator, synthesis or test tool.

		  The course will be conducted over 3 full days and
                  includes comprehensive language training and hands-on
                  exercises.  Each class day will typically contain 5 hours
                  of lecture material and 3 hours of lab.  The course is
                  designed to expose the designer to a detailed overview of
                  the entire complement of syntax and semantics associated
                  with VHDL.  The hands-on exercises have an emphasis on
                  strengthening the understanding of concepts introduced
                  during the lecture sessions.  Each attendee will be
                  provided with a copy of the lecture material, lab
                  exercises workbook, VHDL Language Reference Manual, and
                  VHDL Tutorial.
                                                                                
NOTE:             The course will be taught in an ULTRIX lab environment.
                  If you do not have a basic understanding of ULTRIX or the
                  vi editor, it is recommended that you attend the 2-day
                  "ULTRIX for New Users" course scheduled September 16-17
                  (Course   21CUU-03) or a "compact" ULTRIX U&C scheduled
                  August 26-30 (Course   21CUU-02).
                                                                                
Outline           I.   Introduction to VHDL
                  - Introduce the elements of VHDL notation
                  - Demonstrate how the elements of VHDL fit together in a
                    hardware device model
                  - Compare and contrast the three descriptive styles of
                    VHDL
                                                                                
                  Topics include:
                   A First Example
                   Basic Building Blocks of VHDL Descriptions
                   Structural Description in VHDL
                   Data Flow Description in VHDL
                   Behavioral Description in VHDL
                                                                                
                  II.  Modeling with VHDL
                  - Provide a systematic grounding in al VHDL features and
                    facilities
                  - Provide a thorough working knowledge of signal
                    assignment and process execution mechanisms in VHDL
                  - Inculcate the ability to comprehend and criticize VHDL
                    modeling methodologies
                                                                                
                  Topics include modeling:
                   Simple Data Types
                   Complex Data Types
                   Data Paths
                   Delay
                   Behavior
                   Generic Components
                   Tool Interfaces
                                                                                
                  III. Principles and Definition of VHDL
                  - Explore the fundamental syntactic and semantic notions
                    underlying the design of VHDL
                  - Provide an introduction to the organization and use of
                    the VHDL Language Reference Manual
                  
                  Topics include:
                   Declaration, Scope and Visibility
                   Structural Semantics
                   Behavioral Semantics
                   Elaboration and Execution
                   The Formal Definition of VHDL
 
--------------------------------------------------------------------------------
                  USS/Maynard Area Engineering Training 
			  & E.C.A.D.