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TOOL NAME: Resistance Extractor (REX)
TECHNOLOGY: ELECTRICAL
FUNCTION: Circuit Extractor.
GENERAL DESCRIPTION: Extracts on-chip resistance and capacitance
from node and device DLF files generated by HILEX or IV and calculates
values for those resistors and capacitors. Outputs spice wirelists
with detailed RC models of individual nodes. REX is intended for use
in voltage-drop and metal-migration analysis of IC power and ground nets,
and RC analysis of IC clock and signal nets.
STATUS: Current Release version is V1.2. V1.2 includes capacitance extraction
as well as expanded graphic output. (Previous versions only did resistance
extraction.)
AVAILABILITY: Jan 89. Kit is in CADSYS::CAD$KITS:REX012.A
INTERFACES: REX can output a custom format wirelist for use with the tool
TALENT as well as SPICE-formatted wirelists. The graphic output is viewable
from MEGAN or any other graphic editor capable of reading DLF files.
(A DLF-to-GDSII converter is also available from SEGCAD.)
REX's input is a DLF file for an individual node, typically generated
from IV or HILEX.
CPU/OPERATING SYSTEM: VAX/VMS V4.6 or higher.
SOURCE LANGUAGE: PL/I and C.
ADVANTAGES OF TOOL: REX's output can be used by other tools to provide
further integrity checks and analysis: The voltage drop and path current
of a node can be checked to verify conformance to voltage drop and
electro-migration rules. The capacitance values generated are useful estimates
for timing analysis.
LIMITATIONS OF TOOL: The capacitance apporximation in REX is fairly crude,
and is not generally adequate for accurate loading extimates. (IV and HILEX
can provide more accurate capacitance values.)
RESPONSIBLE ORGANIZATION: SEGCAD, Kent Dalton CADSYS::DALTON (til March 89) or
Dale Donchin CADSYS::DONCHIN.
TRAINING: N/A
DOCUMENTATION: REX manual, 60pp. with many drawings, index. Available from
CADSYS::DOCUMENT, also included in kit as a postcript file.
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