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TOOL NAME: HILEX (HIerarchical Layout Extractor)
TECHNOLOGY: ELECTRICAL (IC layouts)
FUNCTION: layout extractor (generates wirelists from layouts)
GENERAL DESCRIPTION:
HILEX is a general-purpose layout extractor that generates transistor-level
wirelists from IC layouts. It takes MEGAN DLF files as inputs, and can also
take input directly from MEGAN filebases.
HILEX presently has rules files available for Hudson's CMOS-2 and CMOS-3
processes, and also for MLCP package designs and TAB package designs.
HILEX outputs wirelists in two formats, the "CHAS-SPICE" format which is
similar to a SPICE deck, but with signal names instead of numbers, and the
SEG/CAD GWL (Generic WireList) format. The GWL wirelists are generated
in hierarchical form.
A companion capacitance extractor (CUP) is in development.
HILEX is similar in its capabilities to IV, which it is expected to replace.
The primary improvements over IV include:
o 3x to 7x faster run times
o Hierarchical extraction to speed extraction times, and provides
hierarchical output wirelists
o arbitrary-angle processing (IV supports only "manhattan" layout and
45-degree angles.)
o CUP capacitance processing includes lateral capacitance and a more
accurate fringing algorithm. (IV only computes overlap capacitance and
a simple approximation of fringing capacitance.
STATUS
HILEX has been released for production use, but only continuity
extraction capability is available at this time. Limited capacitance
extraction capability will become available during Q2 FY89.
Full hierarchical capacitance extraction for Hudson's CMOS-2 and CMOS-3
processes is expected to be available in Q3 FY89.
Extraction capability for IC packages is in development.
There have been discussions about adding bipolar extraction capability
to HILEX, but this activity is not currently planned or funded.
AVAILABILITY:
A kit is available at CADSYS::LVS$:[HILEX.BASELEVEL.020.KIT]HILEX020.A
(Send mail to CADSYS::HILEX for information on the latest kit.)
INTERFACES:
HILEX is based on MEGAN, and requires that MEGAN be installed first.
CPU/OPERATING SYSTEM:
HILEX runs on VAX/VMS 4.6 or later, including 5.0
SOURCE LANGUAGE:
C (HILEX is layered on MEGAN/MCL/MULTIVIEW, which are in PLI)
ADVANTAGES OF TOOL:
o faster run times
o better options flexibility
o arbitrary angles
o full hierarchical operation
o no limitations on use of hierarchy, i.e. arbitrary cell overlaps are
fully supported
LIMITATIONS OF TOOL:
HILEX virtual memory requirements for full chips are typically somewhat
higher than IV's, since the full hierarchical database is kept in memory.
HILEX text processing and handling of "OPEN"s is somewhat different than
IV's, so there may be slightly different extraction results between HILEX
and IV.
RESPONSIBLE ORGANIZATION:
HILEX is developed and supported by SEG/CAD. Contact CADSYS::HILEX
for more information.
TRAINING:
No training is offered at this time, but a 1-day HILEX course may be
developed later in FY89.
DOCUMENTATION:
A hardcopy HILEX manual is available from CADSYS::HILEX.
A postscript version of the manual is included in the kit as
HILEX_MANUAL_020.POST. Release notes are also included in the kit.
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