| TOOL NAME: Design Rule Checker (DRC)
TECHNOLOGY: Electrical
FUNCTION: Checks the layout of a chip against a set of
design rules to ensure that the layout can result
in a successful fabrication of the chip.
GENERAL DESCRIPTION: Checks that all geometries in the layout of a chip
conform to the specified widths and spacings defined
by the manufacturing technology for the design
process (such as CMOS). DRC uses the design
verification system DRACULA from ECAD Inc.
STATUS: in operation
AVAILABILITY: CADSYS::CAD$KITS; June Cabot (CADSYS::CABOT),Release
INTERFACES: Layout editors, such as MEGAN through DLF files,
and other layout editors, such as the CALMA system,
through files formatted in GDSII stream format
CPU/OPERATING SYSTEM: VAX/VMS
WORKSTATION: Monochrome VWS, color VWS (GPX), VT125, VT240
SOURCE LANGUAGE: PL/I; (ECAD software is in FORTRAN.)
RESPONSIBLE ORGANIZATION: SEG/CAD; Christina Chieng (CADSYS::DRCSUPPORT),
developer
TRAINING: None
DOCUMENTATION: DRC User's Guide
Documentation is available internally by sending
mail to CADSYS::DOCUMENT. ECAD also has its own
documention.
Documentation is not available externally.
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