| TOOL NAME: Interconnect Verifier (IV)
TECHNOLOGY: Electrical
FUNCTION: Analyzes layout and reports potential faults.
GENERAL DESCRIPTION: Extracts a circuit description in the form of a
SPICE-formatted wirelist from a layout file and
reports potential faults relating to nodes and
devices. It also compares data between two
SPICE-formatted wirelists. IV also generates an
ISAM file containing data on nodes and devices and
uses the file to produce a Digital Layout File (DLF)
describing the layout and geometry of specified
nodes and devices.
STATUS: in operation
AVAILABILITY: CADSYS::CAD$KITS; June Cabot (CADSYS::CABOT),Release
INTERFACES: MEGAN through the intermediate file DLF, to SPICE
and other tools producing SPICE-formatted wirelists,
and also interfaces to wirelist converters.
CPU/OPERATING SYSTEM: VAX/VMS
WORKSTATION: no special requirement
SOURCE LANGUAGE: PL/I (main), BLISS, MACRO
RESPONSIBLE ORGANIZATION: SEG/CAD; Alice DiPace (CADSYS::DIPACE), Support
TRAINING: None
DOCUMENTATION: IV User's Guide
Documentation is available internally by sending
mail to CADSYS::DOCUMENT.
Documentation is not available externally.
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