| Title: | Corporate Directory of CAE,CAD,CAM,CIM Tools |
| Notice: | Digital Confidential |
| Moderator: | CADSE::COUPER |
| Created: | Thu Nov 12 1987 |
| Last Modified: | Wed Nov 13 1996 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 122 |
| Total number of notes: | 243 |
AUTODLY - TIMING VERIFIER
SEE 19.1
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 19.1 | AUTODLY - Description | KEATS::CIASCHINI | Thu Sep 08 1988 10:01 | 32 | |
TOOL NAME: AUTODLY
TECHNOLOGY: Electrical
FUNCTION: Timing verifier
GENERAL DESCRIPTION: Timing verifier for synchronous gate-level networks.
It shares DECSIM's user interface (the command
language) and network compiler (NETPRO). AUTODLY
identifies four categories of errors:
o minimum pulse width violations
o data lines that change on the active edge of the
clock or during the setup or hold time of a
device
o edge-to-edge (separation) violations
o overlap violations
It also calculates path lengths.
STATUS: in operation
AVAILABILITY: MR01; Ed Smith (HPSCAD::ESMITH), developer
INTERFACES: DECSIM
CPU/OPERATING SYSTEM: VAX/VMS
WORKSTATION: no special requirements
SOURCE LANGUAGE: BLISS
RESPONSIBLE ORGANIZATION: HPSCAD; Ed Smith, as above
TRAINING: Two day course available; for more
information, contact the ECAD Documentation
& Training Group by sending mail to
ECADSR::COURSES.
DOCUMENTATION: AUTODLY User Guide
Documentation is available internally by sending
mail to ECADSR::DOCUMENT. Please specify
your mail stop.
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