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VAX Layout System Glossary
VAX Layout System Glossary
-------------------------------------------------------
August 1987
August 1987
This document contains definitions for terms commonly
used in the VAX Layout System software and
documentation.
OPERATING SYSTEM: VMS, Version 4.4 or later
OPERATING SYSTEM: VMS, Version 4.4 or later
MicroVMS, Version 4.4 or later
MicroVMS, Version 4.4 or later
SOFTWARE VERSION: VLS, Version 4.2
SOFTWARE VERSION: VLS, Version 4.2
Digital Equipment Corporation
Andover, Massachusetts
For Internal Use Only
First Edition, August 1987
The information in this document is subject to change without notice
and should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.
The software described in this document is furnished under a license
and may be used or copied only in accordance with the terms of such
license.
No responsibility is assumed for the use or reliability of software on
equipment that is not supplied by DIGITAL or its affiliated companies.
Copyright (c) 1987 by Digital Equipment Corporation. All rights
reserved.
The following are trademarks of Digital Equipment Corporation:
DEC MicroVMS RT
DECmate PDP UNIBUS
DECUS P/OS VAX
DECwriter Professional VAXstation
DIBOL Rainbow VMS
MASSBUS RSTS VT
MicroVAX RSX Work Processor
And the Digital logo: -------------
d i g i t a l
-------------
The term SMD is a trademark of the North American Phillips
Corporation.
Preface
Preface
This glossary defines terms and concepts used in VAX Layout System
(VLS) applications and documentation. It also includes the
definitions of surface mount terms that can be found in the draft of
___ ___ ______ ______ _____________ ________ _ _______ _____
DEC STD 030-9, Module Manufacturing Standard - Surface Mount
__________ ______ _____
Technology Design Rules, dated 7/09/87. (This glossary will be
revised after the draft of the standard is reviewed and approved by
the DEC STD 30 Committee.)
NOTE
In some cases, terms used in the printed-wiring board
design environment or VLS design system may differ in
meaning from the same terms used in the manufacturing
environment. Unless stated otherwise, this glossary
includes only those meanings that pertain to the VLS
design environment or the VLS design system.
Intended Audience
Intended Audience
This document defines VLS terms for new VLS users, software
developers, and trainers. In addition, this guide attempts to help
standardize terms to contribute to better communication between board
designers and developers.
Structure
Structure
The definitions appear in alphabetical order. They have not been
grouped into categories.
Associated Documents
Associated Documents
The following documents also define terms used in the design and
manufacture of printed-wiring boards.
iii
___ ___ ______ ______ _____________ ________
DEC STD 030-0, Module Manufacturing Standard, summarizes the module
design rules and practices used to optimize the manufacturing of
modules and backplanes. Section 030-9 of the standard defines
terminology used in surface mount design. (This glossary includes the
definitions provided by the 7/09/87 revision.)
___ ___ ______ ______________ _____________ ___________
DEC STD 016-0, Printed-Wiring Manufacturing Terminology, establishes
terms and definitions in order to assure consistent usage of all
printed-wiring terms which might appear in DIGITAL documents.
_______ ____ _________ ____ _____________
Archive Data Structure File Specification, document identifier
A-SP-ELEN432-00-0, defines the archiving data base (ADS) for the VAX
Layout System and the IDEA II system.
iv
G L O S S A R Y
active:
active: "An element or component, such as a diode or transistor, that
____
does change its basic value when an electrical signal is applied."
_______
From DEC STD 030-9, 7/09/87. See also Passive.
ADS:
_______ ____ _________
ADS: See Archive Data Structure.
Archive Data Structure (ADS):
Archive Data Structure (ADS): A file that contains the physical
description of a printed-wiring board. This file is an ASCII file
intended for long-term storage and its file type is .ADS. You can
use the WRITE ADS application to save the information in the
workspace in a ADS file. New versions of VLS maintain
compatibility with existing ADS files so that a designer can move
work to new versions of the VLS software. However, older versions
of VLS are not necessarily compatible with newer ADS files. (The
ADS file is a corporate standard file used by other CAD/CAM systems
___________ _______ ____ _________
as well as VLS.) See also Environment and Working Data Structure.
area:
area: A closed polygon on one or more layers. VLS designers can
create the following types of areas:
o Board Outline: An area that describes the final trimmed
outline of a printed-wiring board in VLS. (In manufacturing,
_______
this is the circuit outline. See also Circuit.)
o Layer Outline: An area that describes the boundary of a layer.
o Board Cutout: An area that describes a shape that will be cut
out of the design.
o Height Restrict: An area where part height cannot exceed a
specified value.
o Fill: An area that is filled with the material composing the
layer. Conversely, a Fill Void area is void of the material.
o Non-Signal: An area where text and non-signal lines can be
placed. Conversely, a Non-Signal Restrict area cannot contain
____
text or non-signal lines. See also Etch.
1
Glossary
Glossary
o Pad Expansion: An area where pad expansion can occur.
Conversely, a Pad Expansion Restrict area does not allow pad
expansion.
o Placement: An area where components can be placed.
Conversely, a Placement Restrict area does not allow component
placement.
o Routing: An area where connections may be routed. Conversely,
a Routing Restrict area does not allow routing.
o Thieve: An area where thieving pads can be placed.
Conversely, a Thieve Restrict area does not allow thieving
pads.
o Via: An area where vias can be placed. Conversely, a Via
Restrict area does not allow vias.
array:
array: A software structure that stores design information. The WDS
and the workspace are composed chiefly of arrays that are
maintained by VLS programs and require no direct manipulation by
users. The following arrays, which exist in the workspace and the
WDS, are occasionally mentioned in documentation:
o The PART array: Stores all of the information taken from a VBL
file for each part on a design.
o The COMP (component) array: Stores information relating to
individual components on a design, such as component locations,
orientations, and reference designators. (VLS maintains
internal pointers between each component in the COMP array and
the part description stored in the PART array.)
o The NPTD (net-pin/tee data) array: Stores information about
pins and tees. The array maintains a list of the nodes (pins,
tees, and tee/vias) that are included in each network, and
those pins that are not in any network.
o The ASSA (association) array: Stores internal pointers that
correlate information between arrays.
artwork:
artwork: The lines and shapes that form design elements, such as pads
and conductors, and are produced as etch patterns on the
printed-wiring board during manufacturing. Some artwork, such as
the DIGITAL logo, finger patterns (including ZIF fingers), and UL
labels, may be defined and stored in a VBL file.
In manufacturing, artwork usually refers to photographic images
used to produce the working thick-film screens and thin-film masks.
____ _________ _______
See also Etch and VAX-Based Library.
2
Glossary
Glossary
auto thieving:
________ ____
auto thieving: See Thieving Pads.
bendpoint:
bendpoint: A point, other than a pin, tee, or via, where a line
changes direction: for example, a point where two etch segments of
the same signal meet on the same layer. Bendpoints also occur at
the corners of areas and at the corners of annotation lines. See
_______
also Segment.
board:
board: In VLS, a single printed-wiring board (PWB).
In manufacturing, board usually refers to the "production unit"
that goes through module assembly. A single board in module
assembly may hold one or more circuits, depending on the
manufacturing site and circuit size (the circuit size is defined by
the VLS board outline). The term may also refer to a laminate or
_______ ________
to a single printed-wiring board. See also Circuit and Laminate.
bus:
bus: A set of four or more conductors connecting two or more
_________
components. See also Conductor.
CATS:
__________ _________ ____ ______
CATS: See Continuity Automatic Test System.
ceramic leaded chip carrier (CLCC):
ceramic leaded chip carrier (CLCC): "A ceramic, surface mount device
with gull-wing leads along all four edges." From DEC STD 030-9,
7/09/87.
cerquad:
cerquad: "An example of a type of CLCC." From DEC STD 030-9, 7/09/87.
channel:
_________ ________
channel: See Placement Channels.
circuit:
circuit: A VLS term that refers to a network or a portion of a
network. The term is also commonly used to refer to all of the
conductors and nodes on the design.
In manufacturing, circuit refers to a functional printed-wiring
board that has undergone manufacturing processes. Depending on the
size of the circuit, manufacturing may produce several circuits on
a single board. (The circuit size is defined by the VLS board
____ _____
outline). See also Area and Board.
CLCC:
_______ ______ ____ _______
CLCC: See Ceramic Leaded Chip Carrier.
component:
_________ ________
component: See Component Instance.
component instance:
component instance: A part that has been added to a design. A
component instance has component-specific information such as a
location and a reference designator. Any number of component
_____
instances can be based on one part description. See also Array and
____
Part.
3
Glossary
Glossary
component lead:
component lead: A wire, contact, post, or other feature that extends
from a component and serves as a mechanical, electrical, or
electro-mechanical connection between a component and the board.
The component lead is sometimes called a component pin or pin. See
___
also Pin.
component name:
_________ __________
component name: See Reference Designator.
conductor:
conductor: An electrically conductive substance, usually copper, that
remains on a layer after it has been processed in the manufacturing
baths. A conductor carries an electrical current from one node of
a network to another. The conductor width is determined by the
conductor code. In VLS documentation, conductors are frequently
referred to as etch, although DEC STD 30 uses conductor as the more
_________ ____ ____ ____________
accurate term. See also Conductor Code, Etch, Interconnect, and
____
Node.
conductor code:
conductor code: A code, consisting of 1 to 4 characters, that is the
name of a set of conductor attributes. The attributes include
conductor width, conductor end shape, and other conductor
characteristics for every layer of a design. For example, a
conductor code such as ABC could be used to specify a conductor
width of 25-mils for external etch layers, 10-mils for internal
layers, and 0-mils for any layers to which this conductor code does
not apply. A conductor code can be assigned to a network, a
_________
logical connection, or a segment. See also Conductor.
connection:
connection: A logical link between two nodes of a network. (Before
routing, the logical link is often referred to as an unrouted
connection. After routing, the connection is often referred to as
a routed connection. The logical link still exists after it is
____
routed.) See also Node.
Continuity Automatic Test System (CATS):
Continuity Automatic Test System (CATS): A 100-mil grid bed-of-nails
tester used by manufacturing to test for shorts and opens on bare
boards (inner layers as well as composites). Manufacturing also
____
uses other testers with fixed and variable grids. See also Test
_____
Point.
coordinates:
________ _
coordinates: See H-Master 0.
copper sharing:
copper sharing: A process that reduces the number of runs to a pin by
merging a portion of two connections, in the same network, into a
new third connection. For example, two connections that lead to
the same pin could instead be attached to a tee, and a new
connection created between the tee and the pin. See also
__________ ___ ___
Connection, Tee, and Run.
cover:
cover: A set of general information for a VLS design. The cover
includes information such as design data (units, grids, and other
4
Glossary
Glossary
design-specific data), layer description (type, use, routing
direction, size of grids, and other layer-specific data), conductor
codes, holepad codes, pad family codes, and the board defaults for
conductor code and either holepad code or holepad family code. It
also includes areas defined with EDIT AREA. Cover information can
be defined or modified with several VLS applications, including
EDIT COVER and EDIT AREA. (The cover takes its name from the cover
sheet that once accompanied the paperwork for a design.)
Data Link:
Data Link: A set of software tools, including several VLS
applications, that adds manufacturing-specific data such as
thieving pads and soldermask definition. The tools also verify
accuracy of the design and manage the electronic translation and
transfer of data from design sites to manufacturing sites.
Designers can use Data Link to access a WDS and create an MDB and
produce documentation pertaining to the prototyping and release of
_____________ ____ ____
a new printed-wiring board. See also Manufacturing Data Base and
_______ ___________ ____
Product Description File.
data structure:
data structure: A data processing term that is occasionally used to
_______ ____ _________
refer to the WDS. See Working Data Structure.
DEC part number:
DEC part number: The name assigned by DIGITAL to identify a part.
The format of the part number is WW-XXXXX-YY REV ZZZZ, where:
o WW is the Part Class and identifies a general category of
parts.
o XXXXX is the Part Basic and signifies a particular part within
a given part class.
o YY is the Part Variation and is used to indicate that parts are
related but different.
o REV ZZZZ is the Part Revision and identifies different
revisions of a part. The Part Revision is usually preceded by
the expression REV or a semicolon on corporate forms such as
Purchase Specifications. (VLS documentation sometimes refers
to this as the DEC part number revision ID. VLS 4.3 will
support the Part Revision.)
___ ___ ______ ____ ___ ________ ______________ ___________
DEC STD 012-0, Part and Document Identification Conventions,
describes the part number format in detail.
VLS provides two additional identifiers that are used to identify
parts for VLS applications.
o Part description variant, consisting of 0 to 2 alphanumeric
characters, will be supported by VLS 4.3. The part description
variant will be used to identify an alternative description of
5
Glossary
Glossary
the actual part. For example, if there is more than one way of
describing gates within a part, different part files could be
created. Each file would have the same DEC part number
(WW-XXXXX-YY REV ZZZZ), but a different part description
variant.
o Part edit number is the edit number given to the part
description by the EDIT PART LIBRARY application. The number
is automatically incremented by one every time the part
description (the VBL file) is updated with the application.
(This number is specific to VLS; it has no relation to the
VAX/VMS file version number that appears in a VMS directory
listing.)
DEC STD (DEC STANDARD):
DEC STD (DEC STANDARD): A document that describes requirements and
policies for DIGITAL computer products or business practices. The
following standards, and the listed index, are of interest to VLS
designers and developers:
___ ___ ______ ____ ___ ________ ______________ ___________
o DEC STD 012-0, Part and Document Identification Conventions,
states the general policy governing the composition and format
of part and document identifiers.
___ ___ ______ ______________ _____________ ___________
o DEC STD 016-0, Printed-Wiring Manufacturing Terminology,
establishes terms and definitions in order to assure consistent
usage of all printed-wiring terms which might appear in DIGITAL
documents.
___ ___ ______ ______ _____________ ________
o DEC STD 030-0, Module Manufacturing Standard, summarizes the
module design rules and practices used to optimize the
manufacturing of modules and backplanes.
___ ___ ______ _________ _ _______ _________ ____________
o DEC STD 056-0, Symbology - Circuit Schematic Requirements,
defines the requirements for graphic symbols to be used on
circuit schematics in the Engineering Documentation System for
use by Manufacturing, Field Service and customers. The
standard also describes circuit schematic labeling and
interconnection requirements.
___ ___ ______ ______ _____________ _________ _ _____
o DEC STD 140-0, Module Documentation Structure - Basic
____________
Requirements, describes the documentation structure required to
accommodate and control the release of modules, 54-class
assemblies, and printed-circuit (50-class) boards. It also
defines the requirements for the drill and etch format as part
of the 50-level documentation requirements.
___ ___ ______ ______________ _____ __________ ________
o DEC STD 176-0, Printed-Wiring Board Acceptance Criteria,
specifies end-product criteria for rigid printed-wiring boards
that have been fabricated by, or purchased for Digital
Equipment Corporation.
6
Glossary
Glossary
________ ________ _________
o EL-Class Document Directory, document identifier EL-SMDEX-00,
provides the titles, revision dates, abstracts, and expiration
dates of DIGITAL Standards, EL-class specifications, manuals,
and guidelines.
DIP:
____ _______ _______
DIP: See Dual In-line Package.
discrete:
discrete: "A device used as a distinct and individual component and
packaged as a stand-alone element. Diodes and small outline
transistors (SOTs) are examples of discretes." From DEC STD 030-9,
7/09/87.
dispersion pattern:
dispersion pattern: The connections, tee/vias, and conductors (etch)
that are created for a surface mount component pin. Dispersion
patterns serve two purposes. First, they reduce the amount of etch
on outer layers by connecting surface mount component pins to inner
layers. Second, they improve manufacturability by "fanning out"
the connections of surface mount component pins to tee/vias which
are on the via grid. All dispersion patterns include the
following:
o Dispersion connection: The connection (logical link) between a
surface mount component pin, at its mounting pad, and a
dispersion tee/via or other surface feature.
o Dispersion via: A tee/via that is created as part of a
dispersion pattern. (The ADD DISPERSION PATTERNS application
connects a surface mount component pin, at its mounting pad, to
a dispersion via, and shifts the pin's original connections
from the pin to the dispersion via so that the connections can
_______
be routed to inner layers.) See also Tee/Via.
o Dispersion etch: The etch (physical link) between the mounting
pad of a surface mount component pin and a dispersion tee/via
or other surface feature.
dual in-line package (DIP):
dual in-line package (DIP): "A rectangular plastic or ceramic package
for intrusive mounting with two rows of metal leads along its
longer edges." From DEC STD 030-9, 7/09/87.
ECL:
_______________ _____
ECL: See Emitter-Coupled Logic.
edge connector:
edge connector: An electrical contact pattern, generally on the edge
of the board or off the board, that is used to connect the board to
a backplane or other off-module device. Edge connectors, such as a
female socket on a backplane or a female connector on the board
that houses a ribbon cable, are usually created by designers as
artwork parts. The term is frequently used as a synonym for
_______ ______
finger. See also Artwork and Finger.
7
Glossary
Glossary
emitter-coupled logic (ECL):
emitter-coupled logic (ECL): A class of bipolar logic devices in
which the emitters of the input transistors are coupled to the
emitter of a reference transistor. ECL devices, which are commonly
used for high speed products, are normally treed with daisy chain
treeing.
enclosing rectangle:
enclosing rectangle: A rectangle that encloses a part outline and
other geometric features of the part, including the part origin and
part pins. The rectangle, which is not displayed, is calculated by
many VLS applications and used as the part boundary. For example,
the Select options and the SHARK use the enclosing rectangle when
responding to component selection and display requests. In
addition, the term sometimes refers to the box drawn by the SELECT
_____
BY AREA function. See also SHARK.
environment:
environment: A set of software and data elements used to run VLS.
The environment consists of the following elements:
o The applications READ ADS and WRITE ADS
o The VLS public library VLSLIB:VLSPUBLIC.OLB (also identified by
the logical name VLS$VLSPUBLIC)
o The documents ADSSPEC.DOC (Archive Data Structure File
Specification) and WHATSUP.DOC (Working Data Structure -
Programmer's Reference Manual)
o The WORLD, which consists of the following elements:
- VLSMAIN (the VLS Main Menu)
_____
- The SHARK (the Main Graphics Routine) See also SHARK.
______
- VLSRTL (a runtime library) See VLSRTL
- Parameter file (VLS.DAT or VLSSITE.DAT)
- VLS utility programs (READ WDS, WRITE WDS, ADD APPLICATION,
and DELETE APPLICATION)
___ ______ ______
See also VAX Layout System.
etch:
etch: In manufacturing, the process that removes an electrically
conductive substance, usually copper, from the surface of
laminates.
In VLS, etch refers to an electrically conductive substance,
usually copper, that remains on a positive layer or is removed from
a negative layer. VLS documentation refers to the following types
8
Glossary
Glossary
of etch:
o Signal etch: The conductor (etch) that is intended to carry a
signal or current. It is also referred to as interconnect.
o Dispersion etch: The conductor (signal etch) between the
mounting pad of a surface mount component pin and a dispersion
tee/via or other surface feature.
o Non-signal etch: Conductive material (etch) that is not
intended to carry a signal or current. Non-signal etch can be
used for any line on the design that is not carrying a signal:
for example, labeling, inner-layer thieving, and crop marks.
Non-signal etch is also called line data.
o Text etch: Non-signal etch that forms a string of characters,
such as the DIGITAL logo, layer IDs, and polarity markings.
DEC STD 30 uses conductor, instead of etch, as the more accurate
_________
term. See also Conductor.
euclidean length:
euclidean length: The straight line distance between two points. It
is also called straight-line or airline length. Euclidean length
is derived by squaring the vertical length, squaring the horizontal
length, adding the values, and taking the square root. Calculating
euclidean length can take a great deal of processing time, so some
_________
VLS processes use manhattan length instead. See also Manhattan
______
Length.
event:
event: An action that sends information to VLS applications. For
example, an event may be a string of characters followed by a
carriage return or other line terminator, an operation of the
tablet tipswitch, or a VLS keypad function.
"few chip":
"few chip": "A PWB with less than 10 0.050-inch pitch active surface
mount devices on side 1, and without passive devices. See Exhibit
9-4, Major Features of Surface Mount Design Rules, technology level
0.5." From DEC STD 030-9, 7/09/87.
fiducial:
fiducial: A visual reference target, like a bull's eye, created on a
design for surface mount devices and products. Manufacturing uses
the following fiducials for board and component alignment:
o Four circuit-level fiducials, created as single-pin artwork
parts, are placed at the four corners of the board. These
fiducials are used by the optical scanners of assembly machines
as reference targets for rough resolution of board location.
o Two component-level fiducials, created as "fiducial pins" on
the surface mount part, are placed diagonally opposite each
9
Glossary
Glossary
other. These fiducials are used by the optical scanners of
assembly machines as reference targets for fine resolution
before placing or locating components.
DEC STD 030 lists the rules for assigning and placing fiducials on
components and boards.
file type:
file type: The set of characters that follow a file name and a
period. Some operating systems call this set of characters a file
extension. The following briefly describes the meaning of some of
the file types used by VLS applications:
o .ERR indicates a file used to record error messages sent by
some VLS applications. It is like the .LOG file except the
application automatically records the messages in the file.
o .EIF (Engineering Input File) indicates a text file created by
an engineer and added to a VLS design with the application READ
EIF. The file may contain location and mounting information
for components, and routing priorities, routing layer
assignments, and tree types for networks. The file can also be
used to transfer information from one VLS design to another
when major changes to a design make it advisable or necessary
to restart design work.
o .LOG indicates a file used to record information sent to the
terminal screen by VLS. You can specify the types of messages
to be recorded in the file, including fatal, error, warning,
informational, and success messages. You can also specify that
all output sent to the screen be recorded in the file.
o .LGF (Logic Interface Format) indicates a file used for passing
information between a logic design system, such as VALID,
DAISY, or SUDS, and VLS. An .LGF file, which is added to a
design by the application READ LOGIF, describes the
logical-to-physical mapping for a design and contains
identifiers for logic signals and logic functions, and
correlates logic functions with DEC part numbers.
o .RPT indicates a file used to record reports sent by some VLS
applications.
o .TLE (Tabular Logic Editor) indicates a file used to transfer
data from a logic design system such as SUDS, VALID, DAISY, or
SILVAR LISCO to a VLS design. The .TLE file can be used to add
components and networks to a design and to assign pins to
networks. The file, which is added to a design by the
application READ TLE, contains information such as DEC part
numbers, reference designators, pin numbers, and network names.
10
Glossary
Glossary
o .VLJ indicates a journal file that may be used to record all
application commands and options you use during a work session.
You can use the journal file to recover work if a power
interruption or other problem causes you to lose the data in
the workspace.
_______ ____ _________ _______ ____ _________ _________
See also Archive Date Structure, Working Data Structure, workspace,
_________ _______
and VAX-Based Library.
finger:
finger: An electrical contact shape, located at the edge of the
board, that is used to connect the board to an edge connector
provided by a backplane or other off-module device. Fingers are
usually created by the designers as artwork parts. Because fingers
are located at the edge of the board, they are frequently referred
to as edge connectors. In addition, ZIF (zero insertion force)
_______
connectors are referred to as external connectors. See Artwork and
____ _________
Edge Connector.
footprint:
footprint: The set of pads located where the pins of a surface mount
component make electrical contact with the board.
footprint pad:
footprint pad: "A surface mount pad on which a component is mounted
and soldered." From DEC STD 030-9, 7/09/87.
gate:
gate: An independent function performed within a part, such as an AND
gate. VLS uses gate definitions to support gate swapping. For
example, one of the four AND gates in a single package could be
swapped with another AND gate within the same part or an identical
____ ___ ____
part. See also Gate Leg and Swap.
gate leg:
gate leg: A logic pin that belongs to a logic function (gate). See
____
also Gate.
grid:
grid: "A pattern of horizontal and vertical lines forming squares on
a surface that is relative to H-Master 0 (0,0 component origin)."
From DEC STD 030-9, 7/09/87.
VLS applications allow design elements, such as component pins,
vias, conductors, test points, and text, to be placed on or in
relation to a grid. VLS creates grids relative to VLS origin, and
the programs that translate VLS coordinates to manufacturing
________ _
coordinates also preserve grid locations. See also H-Master 0.
gull-wing lead:
gull-wing lead: "A lead that exits the body of a component parallel
to the bottom of a package, then forms a right-angle bend, and
finally another right-angle bend." From DEC STD 030-9, 7/09/87.
H2D/50:
H2D/50: "Two conductors between pads having vias on 0.050-inch
_____
centers." From DEC STD 030-9, 7/09/87. See also HD/50.
11
Glossary
Glossary
HD/50:
HD/50: "One conductor between pads having vias on 0.050-inch
______
centers." From DEC STD 030-9, 7/09/87. See also H2D/50.
H-Master 0:
H-Master 0: "The 0,0 default datum." From DEC STD 030-9, 7/09/87.
H-Master 0 is the origin (0,0) of the coordinate system used by
manufacturing systems which view the design from side 2 (the bottom
side). By historical convention in DIGITAL, H-Master 0 is defined
to be 2.7 inches to the right of and 1.7 inches down from the lower
right corner of side 1 of the board.
The origin (0,0) of the VLS coordinate system is 23.2 inches to the
left of H-Master 0, at the same Y.
The WRITE PDF and MDB WRITER applications translate VLS coordinates
into manufacturing coordinates based on H-Master 0. These
coordinates are used in communications from manufacturing and in
_______
some output from the MDB WRITER application. See also Product
___________ ____
Description File.
holepad code:
holepad code: A code, consisting of 1 to 4 characters, that is the
name of a set of attributes for a pad-hole combination. The
attributes include the diameter of a hole and the surrounding pad
shapes and sizes for each layer of the design. Holepad codes may
be assigned to pins, vias, and tees. The holepad code is sometimes
called the hole code or hopa code, and the set of pads surrounding
the hole is sometimes called the padstack.
A null holepad has no hole and no pads. Routing tools assign the
null holepad code to a pin or tee that requires a holepad code, but
an actual hole or pad is not wanted. For example, two surface
mount pins that reside at the same X,Y location, on opposite sides
of the board, can share a through-via when the pins are in the same
network and have the same holepad code. The routing tools replace
one of the "real" holepad codes with the null holepad code so that
_______
only one holepad is built in manufacturing. See also Holepad
______ _______ ___
Family, Tee/Via, and Via.
holepad family:
holepad family: A set of holepad codes, identified by a name, that is
used to connect different combinations of layers. The holepad
family specifies both the applicable layer range of each holepad
and an ordered set from which a holepad can be selected for each
individual layer pair. A holepad family can be assigned to the
same items as a single holepad code, including design default,
networks, pins, and vias.
Holepad families are very useful when one of several holepad codes
can be assigned to a pin, tee, or a via, depending on the layers
that the pin, ptee, or via must connect. The holepad family allows
the holepad code assigned to the pin, tee, or via to be changed as
12
Glossary
Glossary
routing operations change the required layer range of the pin,tee,
or via. For example, when a new connection is routed to a pin on a
given layer, the holepad code assigned to that pin may be changed
from one to another within the family that includes this new range.
Holepad families are commonly used for designs where blind or
buried vias are available. The code for a family is commonly
_______ ____
referred to as a pad family code or PFAM. See also Holepad Code.
hopa:
_______ ____
hopa: A synonym of holepad code. See Holepad Code.
hybrid/carrier:
hybrid/carrier: A package type that indicates a rectangular package
_______ ____
other than a DIP or SIP. See also Package Type.
IC:
__________ _______
IC: See Integrated Circuit.
insertion code:
insertion code: A 2-character code, generally assigned by Component
Engineering, that indicates to manufacturing how a component may be
placed on a board. For surface mount devices, the code is
sometimes referred to as an onsertion code. Insertion codes may be
included in a VBL file. Rules for assigning insertion codes are
contained in Engineering Specification A-SP-7665228-00-0, Component
Categories and Codes for Machine and Non-Machine Insertable
Components. New rules can be found in the SPOC Data Base. See
_________ _______
also VAX-Based Library.
integrated circuit (IC):
integrated circuit (IC): A combination of connected circuit elements
linked on or in a continuous substrate. A typical IC is a packaged
silicon chip.
interconnect:
interconnect: Any substance or medium, such as a wire or a conductor,
that carries a current of electricity from one node to another.
_________ ____
See also Conductor and Etch.
intrusive pin:
intrusive pin: A pin that is mounted on a board by inserting it into
a through-hole and soldering it on the opposite side of the board,
____________ ___
almost always side 2. See also Through-Hole and Pin.
J-bend lead:
J-bend lead: "A lead that exits the body of a component and then
bends down the side and under the body of the component package."
From DEC STD 030-9, 7/09/87.
laminate:
laminate: A product made by bonding two or more layers of material;
for example, a fiberglass sheet impregnated with resin and covered
on one or both sides with copper foil.
laminated stencil:
laminated stencil: "A laminated, or stepped, stencil is a stencil of
two thicknesses used for applying solderpaste when mixing
0.050-inch and 0.025-inch pitch components." From DEC STD 030-9,
7/09/87.
13
Glossary
Glossary
layer:
layer: One surface of a sheet of material, such as copper, ink, or
soldermask. Design elements such as components, pads, conductors
(signal etch), text etch, and areas are assigned to particular
layers. The number and type of layers, such as signal layers,
power and ground layers, and soldermask layers, depend on design
requirements. VLS displays layers as if they were a series of
overlaid transparencies, and you may turn the display of specified
_____
layers on and off. See also Layup.
layup:
layup: A drawing that shows layer order, dimensions, and types for a
printed-wiring board. Standard layups exist for typical
printed-wiring boards, such as a single sided, non-plated
through-hole board; a double sided, plated through-hole board; or a
_____
multilayer 4-layer board. See also Layer.
LBV:
_______________ ___
LBV: See Laminated-Blind Via.
LCCC:
________ _______ ____ _______
LCCC: See Leadless Ceramic Chip Carrier.
leadless ceramic chip carrier (LCCC):
leadless ceramic chip carrier (LCCC): "A leadless ceramic chip
carrier with gold contacts that solder directly to the footprint
pad. LCCCs shall not be used. Refer to Rule 9050." From DEC STD
030-9, 7/09/87.
leg function:
leg function: General function of a specific gate leg, such as input
and output. The leg function is stored in the part description
____ ____ ___
(VBL file). See also Gate and Gate Leg.
load pin:
load pin: An input to a function (gate) within a part: for example,
____ ____ ___
the clock input of a counter. See also Gate and Gate Leg.
macro cell array (MCA):
macro cell array (MCA): An IC that has 1,000 to 10,000 gates, grouped
into clusters, and a large number of I/O pins. VLS supports the
use of packages carrying MCAs on a printed-wiring board and, within
certain constraints, the design of MCAs, including the connection
___ ____ _____
and routing between gates. See also Pin Grid Array.
manhattan length:
manhattan length: A length obtained by adding the vertical and
horizontal distance between two points. Manhattan length is a
useful measure of the distance between two points, such as the end
points of a logical connection, because conductors are often
required to travel only horizontally or vertically. See also
_________ ______
Euclidean Length.
Manufacturing Data Base (MDB):
Manufacturing Data Base (MDB): A data base, used by manufacturing,
that contains manufacturing data for a design. The MDB WRITER
application can create the set of files that comprise the MDB from
the information in the WDS. In addition, STREAM can create an MDB
from the information in the PDF. (The MDB is a corporate standard
____ ____
data base used by several CAD/CAM systems.) See also Data Link,
14
Glossary
Glossary
_______ ___________ ____ ____ ____ _______ _________ ___
Product Description File, and Soft Tool Release Executive And
____________
Manufacturer.
MCA:
_____ ____ _____
MCA: See Macro Cell Array.
MCU:
________ ____ ____
MCU: See Multiple Chip Unit.
MDB:
_____________ ____ ____
MDB: See Manufacturing Data Base.
MELF:
MELF: "A cylindrical surface mount device with contacts on both ends.
MELFs are not recommended for new designs." From DEC STD 030-9,
7/09/87.
mixed mount:
mixed mount: "Use of surface mount components in conjunction with
intrusive components." From DEC STD 030-9, 7/09/87.
module:
module: The completed printed-wiring board, including components.
_____ _______
See also Board and Circuit.
mounting pad:
mounting pad: A surface mount pad that a device pin is bonded to.
_________
See also Footprint.
mounting values:
mounting values: Three values -- Mounting Type, Allowable Mounting
Layers, and Inverse Mountable -- that indicate how a part may be
mounted on a board. These values are stored in a VBL file.
Mounting Type: One of the following values is used to specify how
the part pins of physical and temporary parts are attached to the
board.
o Intrusive Pin: The pins of the part are inserted into
through-holes and soldered on an external side, almost always
side 2.
o Surface Mount: The part pins are bonded to solder pads that
are built on the board surface.
o Socket Mount: The pins of the part may only be attached to
another part, which must be a socket.
o Unknown: The mounting type is unknown or not applicable.
Allowable Mounting Layers: One of the following values is used to
specify on which layers of the board the part may be mounted.
o From Top: May be mounted on the top side of the board only.
o From Top and Bottom: May be mounted on the top or bottom side
of the board.
15
Glossary
Glossary
o From Bottom: May be mounted on the bottom side of the board
only.
o From Any: May be mounted on any layer.
o Unknown: The allowable mounting layers are unknown or not
applicable.
Inverse Mountable: Yes or No is used to specify whether a part may
be mounted upside down.
o Yes: A temporary or physical part may be mounted upside down
on a surface in addition to being mounted right-side up on the
same surface. An artwork or assembly macro part can be
mirrored (flipped about the y-axis prior to any rotation).
o No: Inverse mounting is not allowed.
multiple chip unit (MCU):
multiple chip unit (MCU): A multiple silicon substrate in one
package. The MCU is at a level between the chip and the
traditional printed-circuit module and is treated as a module in
the hardware structure and documentation.
neighborhood:
neighborhood: A set of components used by the component swappers to
reduce the length of connections on the board. The ROUGH swapper
uses neighborhoods of 36, 20, 12, and 8 components. The FINE
swapper uses neighborhoods of 24, 12, and 8 components. See also
____
Swap.
net type:
net type: One of the following values, assigned in EDIT LOGIC, that
describes how a network is used:
Power
Ground
Logic
Non-functional
Not-defined
Other
Analog
Clock
network:
network: A set of nodes and conductors that forms a complete
electrical path on a printed-wiring board. A network may also
include in-line components such as terminating resistors. A
___ ____
network is also referred to as a net. See also Net Type.
node:
node: A pin or tee in a network. After the network has been treed, a
__________
node is the end point of a connection. See also Connection,
_______ _______
Network, and Treeing.
16
Glossary
Glossary
null holepad code:
_______ ____
null holepad code: See Holepad Code.
ohmega technology:
______ ________ __________
ohmega technology: See Planar Resistor Technology.
onsertion:
onsertion: The process of placing surface mount components on the
_________ ___ _______ _____ __________
board. See also Footprint Pad and Surface Mount Technology.
outline:
outline: A closed boundary. VLS uses the following outlines:
o Component Outline: A two-dimensional, visual representation of
a part package that is stored in the part definition (VBL
file). The outline is drawn on the graphics screen by VLS
applications and is also used in documentation drawings
produced by EDIT DRAWING and PLOT.
o Board Outline: The boundary of the final trimmed board. The
board outline is defined with the EDIT AREA application. (AUTO
THIEVING documentation refers to this outline as the Circuit
Outline.)
o Layer Outline: The boundary of a layer. Layer outlines are
____
defined with the EDIT AREA application. See also Area.
package envelope:
package envelope: "The outline of the entire body and lead extreme
with the exception of the horizontal portion of the gull-wing lead,
as applied to rule 9710." From DEC STD 030-9, 7/09/87.
package name:
package name: The characteristic of a part that identifies the
particular type of physical package carrying the part, such as
SOIC8 (8-pin small outline dip), PLCC44 (44-pin plastic leaded chip
carrier), or PLCC16 (16-pin plastic leaded chip carrier). The
package name is stored in the part definition (VBL file). See also
_______ ____
Package Type.
package type:
package type: The characteristic of a part that indicates the type of
generic package that contains the part. Package type may affect
manufacturability. It can be specified as CAN, DIP, SIP, AXIAL,
RADIAL, HYBRID/CARRIER or OTHER. The package type is stored in the
_______ ____
part definition (VBL file). See also Package Name.
pad:
pad: A portion of a conductive pattern that is usually employed to
connect components to the board. Pads are placed at the mounting
locations of surface mount pins, at some tees, and within vias to
ensure good contact between conductors, pins, and vias. (Some
pads, such as pads on negative layers, are used to prevent contact
_________ ___ _______ ____
with copper on a layer.) See also Footprint Pad, Holepad Code, and
________ ___
Mounting Pad.
pad expansion:
pad expansion: The process of enlarging a pad, in the direction of
the connecting conductor, to compensate for possible off-drilling
17
Glossary
Glossary
___
in manufacturing. See also Pad.
pad family:
_______ ______
pad family: A synonym for holepad family. See Holepad Family.
pad layer:
pad layer: "The outermost layers of a PWB having pads; SMT component
footprints with dispersion patterns to the vias, and short
connections to test pads and edge connectors." From DEC STD 030-9,
7/09/87.
padstack:
padstack: The set of pads and the hole specified by a holepad code.
_______ ____
See Holepad Code.
part:
part: A physical element used on a printed-circuit board, such as an
IC, transformer, capacitor, or handle. In addition, some design
elements are defined as parts although they are created during
manufacturing, including the DIGITAL logo, circuit-level fiducials,
and fingers. The electrical, physical, and functional information
_________
that describes a part is stored in a VBL file. See also Component
________ _________ _______
Instance and VAX-Based Library.
part description:
part description: A term commonly used to refer to all of the
information in a VBL file or the PART array that describes a part.
_____ ____ _________ _______
See also Array, Part, and VAX-Based Library.
part description variant:
part description variant: A character string used to identify an
___ ____ ______
alternative description of a part within VLS. See DEC part number.
part edit number:
part edit number: An edit number for a part description (VBL) file
that is incremented by one every time the description is updated
___ ____ ______
with the EDIT PART LIBRARY application. See DEC part number.
part library:
part library: A VMS directory used to store one or more VBL files.
The term occasionally, but inaccurately, refers to a VBL file. See
_________ _______
also VAX-Based Library.
passive:
____ ___
passive: "An element or component that does not change its basic
value when an electrical signal is applied, for example; an
inductor, resistor, or capacitor." From DEC STD 030-9, 7/09/87.
______
See also Active.
PDF:
_______ ___________ ____
PDF: See Product Description File.
PFAM:
_______ ______
PFAM: A synonym of holepad family. See Holepad Family.
PGA:
___ ____ _____
PGA: See Pin Grid Array.
pin:
pin: A wire, contact, post, or other feature that extends from a
component and serves as a mechanical, electrical, or
electro-mechanical connection between a component and the board. A
_________ ____
pin is also called a component lead. See Component Lead.
18
Glossary
Glossary
pin function:
___ ________
pin function: See Leg Function.
pin grid array (PGA):
pin grid array (PGA): A part package that has intrusive pins arranged
in a two-dimensional grid-like pattern. A PGA is used as a package
for a large or customized IC. For example, a 72-pin PGA is often
_____
used as the package for an MCA (macro cell array). See also Macro
____ _____
Cell Array.
pin rotation:
pin rotation: A process that rotates the pads of selected surface
mount component pins a specified number of degrees. By convention,
rectangular and line-shaped pads are originally defined with their
long side parallel to the X-axis (that is, a rotation of 0). After
a component is placed on a design, the pads of selected pins may be
_________ ________
rotated to eliminate overlapping. See also Footprint and Mounting
___
Pad.
pin values:
pin values: The miscellaneous properties of part pins, such as Rise
Time of Signal and Maximum Allowable Delay. The values are stored
_________ _______
in the part description (VBL file). See also VAX-Based Library.
pitch:
pitch: "The distance between two or more corresponding points such as
the distance between pins on a component." From DEC STD 030-9,
7/09/87.
When creating a part definition with the VLS application EDIT PART
LIBRARY, you can define the distance between pin centers by using
the LINEAR/MATRIX option and entering horizontal pitch and vertical
pitch.
placement channels:
placement channels: A set of rows and columns that overlays a design
as an aid to component placement. The placement functions position
components so that each part origin is located at the intersection
of placement channels.
planar resistor technology:
planar resistor technology: A technology that uses a layer of
resistive material instead of discrete parts to produce resistors.
The layer of resistive material is referred to as a planar resistor
layer. The resistive material is most often used as terminating
resistors. (Planar resistor technology has often, but
inappropriately, been called Ohmega technology, a term derived from
the vendor Ohmega Technologies Inc.)
plastic leaded chip carrier (PLCC):
plastic leaded chip carrier (PLCC): "A plastic package with leads
along at least two edges." From DEC STD 030-9, 7/09/87.
PLCC:
_______ ______ ____ _______
PLCC: See Plastic Leaded Chip Carrier.
power/ground:
power/ground: The functions assigned to pins, layers, and networks
that supply electrical current to the board or are connected to a
power or ground network.
19
Glossary
Glossary
Product Description File (PDF):
Product Description File (PDF): A file used to transfer a design to
manufacturing. The file contains the description of a complete
design based on a final WDS file and its file type is .PDF.
Manufacturing may use the PDF to build an MDB. (The PDF file is a
corporate standard file used by other engineering systems as well
________ _ _______ ____ _________
as VLS.) See also H-Master 0, Working Data Structure, and
_____________ ____ ____
Manufacturing Data Base.
PWB:
_____ _______
PWB: See Board Circuit.
reference designator:
reference designator: A unique name given to every component on a
design. The leading characters in a reference designator identify
the component type, and the trailing numeric characters give a
unique identification for a particular component type on the
design. For example, in the designators C1 and C2, C stands for
capacitor and 1 and 2 are the unique numeric assignment. The
reference designator is sometimes called the component name. See
_________ ________
also Component Instance.
router:
router: A set of tools that creates conductors (signal etch) to
physically implement logical connections. Generally, these tools
are complex applications that attempt to maximize the number of
connections they are able to complete and to minimize the amount of
conductive material (etch) used by each connection.
The routing tools use information such as areas, holepad codes,
holepad families, and conductor codes to determine the path of the
_______ _____ ___
physical interconnect. See also Treeing, TWIGY, and Via.
run:
run: One or more contiguous segments of conductive metal (signal
etch), on one layer, that terminates at each end on either a node
or via. For example, the route (signal etch) between two pins or a
_______ _________
pin and a tee/via is a run. See also Segment and Conductor.
segment:
segment: A straight line of route (signal etch) between two points,
where a point may be a pin, tee, via, or bendpoint. See also
_________
Bendpoint.
SHARK:
SHARK: A set of VLS routines that control the display of the design.
This set of routines is also referred to as the Main Graphics
Routine. The SHARK TAILS are a set of device-specific routines
that receive information from the SHARK and send it to the local
___________
graphic devices. See also Environment.
side:
side: The outermost surfaces of the board. Side 1 refers to the top
surface of a design; side 2 refers to the bottom surface of a
design.
small outline integrated circuit (SOIC):
small outline integrated circuit (SOIC): "A package resembling a DIP,
but shorter and flatter with gull-wing leads." From DEC STD 030-9,
20
Glossary
Glossary
7/09/87.
small outline J-bend (SOJ):
small outline J-bend (SOJ): "A small outline package with J-bend
leads on two sides." From DEC STD 030-9, 7/09/87.
small outline transistor (SOT):
small outline transistor (SOT): "A small outline transistor with two
gull-wing leads on one side and one on the opposite side." From DEC
STD 030-9, 7/09/87.
SMT:
_______ _____ __________
SMT: See Surface Mount Technology.
Soft Tool Release Executive and Manufacturer (STREAM):
Soft Tool Release Executive and Manufacturer (STREAM): A CAM system
that can produce and read an MDB (Manufacturing Data Base) and use
the information to produce device-specific data that drives
manufacturing equipment such as drill, router, and insertion
machinery. STREAM will be replaced in the future by MIDAS. See
_____________ ____ ____
also Manufacturing Data Base.
software problem report (SPR):
software problem report (SPR): A report of a problem or error found
in VLS software or documentation. The form used to describe such
problems to CADSE is also called the Software Problem Report.
SOIC:
_____ _______ __________ _______
SOIC: See Small Outline Integrated Circuit.
SOJ:
_____ _______ ______
SOJ: See Small Outline J-bend.
soldermask:
soldermask: A permanent polymer coating (wet mask) or film (dry film
mask) that is photo-resistive. Soldermask is added to one or both
sides of a printed-wiring board to prevent solder shorts in the
manufacturing baths of molten solder and to prevent oxidation of
exposed conductive material during the life of the board. The ADD
SOLDERMASK application generates soldermask information.
SOT:
_____ _______ __________
SOT: See Small Outline Transistor.
source pin:
source pin: An output of a function (gate) within a part. See also
____ ____ ___
Gate and Gate Leg.
SPR:
________ _______ ______
SPR: See Software Problem Report.
STREAM:
____ ____ _______ _________ ___ ____________
STREAM: See Soft Tool Release Executive and Manufacturer.
string:
string: A set of alphanumeric characters treated as a unit of text;
for example, text etch is made up of strings.
stub:
stub: A line of route (etch) that branches off from the main path of
a network to provide a connection to a pin or test pad. In
addition, a stub may be a line of etch between a node and a tee
______
that is created to provide copper sharing. See also Copper
_______
Sharing.
21
Glossary
Glossary
substrate technology:
substrate technology: The technology of laminants and other types of
materials that serve as a base platform for components and
interconnect. Substrate technology includes Micro Substrate
technology, which builds multilevel thin film interconnections on a
ceramic substrate (base), to produce high density interconnect
systems for multiple, high performance ICs. A Micro Substrate
device can be treated as a component and mounted on a
printed-wiring board. (The term substrate is frequently used to
refer to Micro Substrate technology.)
Surface Mount Device (SMD):
Surface Mount Device (SMD): "A device that is mounted directly onto
the surface pad area of a PWB." From DEC STD 030-9, 7/09/87.
surface mounting (non-intrusive):
surface mounting (non-intrusive): "A method of attaching an
electrical component directly to the surface pad areas of a PWB."
From DEC STD 030-9, 7/09/87.
Surface Mount Technology (SMT):
Surface Mount Technology (SMT): A technology that places parts on a
board by attaching component leads to the module without the use of
intrusive pins. Within DIGITAL, SMT has evolved through the
following versions:
o Versions 0.5, 1.0, and 1.5 are early releases of surface mount
capability, of medium density, that support a mix of 50-mil
pitch surface mount parts with conventional intrusive parts in
an essentially single-sided design. Discrete passive parts are
allowed on side 2.
o Versions 2.0 and 2.1 support a high-density design that uses
50-mil pitch surface mount parts in a fully double-sided
design. In order to achieve this high density it is necessary
to either apply the technique to highly bussed designs or to
use laminated blind vias, and to severely curtail the use of
intrusive parts to meet module assembly capabilities.
o Versions 2.2 and 2.3 support even higher densities by allowing
25-mil pitch surface mount parts but applying even more
restrictions to the mix of other types of part.
Refer to DEC STD 030-9, Module Manufacturing Standard - Surface
Mount Technology Design Rules, for a full definition of surface
mount capabilities.
swap:
swap: The exchange of identical components, gates, and pins to reduce
the length of connections and improve routability.
The ROUGH component swapper swaps the location of each component
with sets of 36, 20, 12, and 8 neighboring components and leaves
the components in the new locations if the total connection length
of all connections attached to each component is reduced. The FINE
22
Glossary
Glossary
component swapper swaps the location of each component with sets of
24, 12, and 8 neighboring components and leaves the components in
the new locations if the total length of all networks on the pair
of components is reduced.
The gate swapper, much like the FINE component swapper, swaps the
locations of a pair of gates and retrees all of the gates before
and after swapping. The gates are left in the locations that
result in the shortest length. The swapper attempts exchanges of
gates that belong to identical components.
The pin swapper works like the gate swapper, except it swaps only
pin pairs within a gate, never across gates or components.
tee:
tee: A location where connections meet, other than at a pin. If a
_______
tee is assigned a holepad code, it is a tee/via. See also Tee/Via.
tee/via:
tee/via: A tee that has a holepad code assigned to it. The holepad
code may define a set of pads and the corresponding hole or simply
a pad with no hole, but in either case, the tee is a tee/via.
Tee/via often appears in documentation as "tee with a via." See
_______ ____ ___
also Holepad Code and Tee.
tenting:
tenting: The process of completely covering a via with soldermask.
Tenting can occur only in a dry-film process, over a via that is
__________
not used as a test point. See also Soldermask.
termination band:
termination band: "Metal conductors located at the end of a chip
component for attachment to footprint pads on a PWB." From DEC STD
030-9, 7/09/87.
terminator pin:
terminator pin: The last pin in a network. The terminator pin is
usually a resistor pin or a resistor-type component pin that
reduces electrical reflections at the end of network route.
Terminators are often needed for networks containing open-emitter
ECL pins and open-collector TTL pins.
test pad:
test pad: A pad used as a test point. The pad is a conductive area
that is attached to a circuit feature. The pad may be a tee/via,
with a pad but no hole, on the outermost etch layer. Test pads may
be created by the EDIT TEST POINTS or SETUP TEST POINTS
____ ____ _____
applications. See also Stub and Test Point.
test point:
test point: A point such as a pin, via, or test pad where a test
probe may be placed to inject or sample a signal. Test points are
probed during the manufacturing process to detect short circuits,
broken connections, and other electrical faults on a circuit. See
____ ___
also Test Pad.
thieving pads:
thieving pads: Non-functional copper pads placed on surface or inner
23
Glossary
Glossary
etch layers in large spaces where there is no copper (hole pads or
etch artwork). The thieving pads, which are added to make the
copper per unit-area constant across the entire surface of the
layer, protect the routes near the empty spaces from being thinner
than intended or entirely etched away in the manufacturing process
baths. The AUTO THIEVING application is used to create thieving
pads.
through-hole:
through-hole: A hole that passes from one board side to another.
(The term through via is frequently, but inappropriately, used as a
synonym for a through-hole used by an intrusive pin.) See also
_________ ___ ___
Intrusive Pin and Via.
through-hole mounting (intrusive):
through-hole mounting (intrusive): "A method of attaching a component
to a PWB using a lead and a plated-through hole." From DEC STD
030-9, 7/09/87.
tree:
tree: The ordered list of all connections in a network. A tree is
_______
also called the connection tree. See Treeing.
treeing:
treeing: A VLS process that creates and orders the logical
connections between pins in a network. The treeing process uses
part, pin, and network data supplied by engineering and creates the
connections (logical links) between pins in selected networks. The
tree type specified for a particular network determines how
__________ ____
connections can be made between pins. See also Connection and Tree
____
Type.
tree type:
tree type: A treeing option that determines the path of logical
connections between the pins in a network:
o Min Span: Connects the pins of a network to form a path of
minimum physical length (the sum of pin-to-pin distances). Min
span treeing allows a single pin to be directly connected to
any number of other pins; it is always used for
transistor-transistor logic (TTL).
o Daisy Chain: Connects the pins of a network to form a single
path of minimum physical length (the sum of its pin-to-pin
distances). Daisy chain treeing allows a single pin to be
directly connected to one or two other pins; it is always used
for emitter-coupled logic (ECL).
o Random: Connects the pins of a network in the order that they
appear in the WDS. Random treeing can be used for a very large
network that would consume too much time or memory if min span
or daisy chain treeing were requested.
transistor-transistor logic (TTL):
transistor-transistor logic (TTL): A class of bipolar logic devices
in which the emitters of a multiple emitter transistor serve as the
24
Glossary
Glossary
logic gate inputs. TTL devices are normally treed with min span
treeing.
TTL:
_____________________ _____
TTL: See Transistor-Transistor Logic.
TWIGY:
TWIGY: The original name of the AUTO ROUTE application. The name
TWIGY is derived from Twin Line Geometry, a router that ran on the
PDP-10. The name VTWIGY derives from the same router that ran on
VAX systems. The names TWIGY and VTWIGY frequently appear in
documentation and are also used in the file names of software and
______
documentation related to AUTO ROUTE. See also Router.
units:
units: Values that specify the unit of measure, in inches or meters,
for the display, design, and archiving of a design. The following
values are specified with the EDIT COVER application at the start
of the design process:
o Display Unit specifies the units of measure in which
coordinates and distance are displayed.
o Design Unit specifies the unit of measure and resolution of
coordinate values used to store data in WDS files written from
the workspace. (This is sometimes referred to as the internal
unit.)
o Archive Unit specifies the unit of measure and resolution of
coordinate values used to store data in ADS files written from
the workspace.
_____
See also Cover.
VAX-Based Library (VBL):
VAX-Based Library (VBL): A file that contains the electrical,
physical, and functional information that describes a part for use
____
by VLS. See also Part.
VBL:
_________ _______
VBL: See VAX-Based Library.
via:
via: A means of passing a signal from one board layer to another. In
VLS, the automatic or manual routing tools add vias to a design by
assigning a holepad code to a node or to the end of a run where it
is necessary or desirable to pass a signal to a different layer.
The holepad code defines the layer range and other characteristics
of the via.
In manufacturing, a via is created by drilling a hole, adding pads,
and plating or filling the hole according to the specifications of
the holepad.
The following types of vias are supported by VLS:
25
Glossary
Glossary
o Through via - A means of passing a signal through all layers of
a printed-wiring board. A through via is manufactured as a
plated through-hole that connects all layers of a
printed-wiring board. A through via extends between both sides
of the board.
o Blind via - A means of passing a signal from an outer layer of
a board to the inner layers. A blind via is manufactured at
DIGITAL by creating a through via in a board subassembly. A
blind via is visible from only one side of the board.
o Buried via - A means of passing a signal between inner layers
of the board. A buried via is manufactured by creating a hole
that starts at an inner layer and stops at a different inner
layer. Buried vias are not visible from either of the outer
layers of a board. As a general rule, buried vias can be
constructed only between opposite sides of the same laminate.
o Staircase via - One of a series of blind or buried vias that
compose a staircase. A staircase connects the pins of a
surface mount component to inner layers. A staircase is used
specifically for those technologies, such as substrate
technology, that limit vias to passing through a certain number
of layers. Each via created in a staircase can be assigned a
holepad code so its layer range includes a certain number of
layers, thus allowing the pin's connection to "staircase" down
to inner layers. A holepad family can be used to specify the
vias that compose a staircase.
The following terms are also used to describe vias in VLS
documentation and in DEC STD 30-9:
o In-line via - A via with a pad diameter smaller than or equal
to the width of the conductor that meets it.
o In-run via - A via that is not a node. That is, the via occurs
at the end of a run, but it is not the end of a logical
connection. An in-run via is also referred to as an
in-connection via or a pure via.
o Laminated-blind via (LBV) - "A via structure that extends from
one surface to the midpoint of a symmetric lay-up. A board
suitable for laminated-blind via construction must have at
least two signal layers associated with each half of the board,
and two pad layers." From DEC STD 030-9, 7/09/87.
o Mini via - "A via of 0.013-inch drill size with a 0.025-inch
pad and a 0.010-inch finished hole size." From DEC STD 030-9,
7/09/87.
26
Glossary
Glossary
o SMT via - "A through-via of 0.025-inch drill size with a
0.040-inch pad and a 0.020-inch finished hole size." From DEC
STD 030-9, 7/09/87.
o Tented via - "A via that is covered with dry film soldermask so
as to seal the drilled hole." From DEC STD 030-9, 7/09/87.
____________ _______ _____ ____
See also Through-Hole, Holepad, Layer and Node.
VAX Layout System (VLS):
VAX Layout System (VLS): A CAD system that consists of a common
environment and approximately 65 applications used to lay out
___________
printed-wiring boards. See also Environment.
VLS:
___ ______ ______
VLS: See VAX Layout System.
VLSLIB:
VLSLIB: The logical name of a directory that contains many of the
files required to run the current version of VLS.
VLSRTL:
VLSRTL: A runtime library that contains many of the software routines
that may be called by VLS applications. This name often appears in
___________
messages sent by VLS. See also Environment.
WDS:
_______ ____ _________
WDS: See Working Data Structure.
window:
window: The region of a design to be displayed. It is also the name
of a VLS keypad function that allows you to control the display of
a design. WINDOW lets you zoom in and out, center the display
about any selected point or component, and save and restore several
views of the design.
Working Data Structure (WDS):
Working Data Structure (WDS): A file that contains the description of
a printed-wiring board currently being designed. This file is a
binary file intended for short-term storage and routine backup of
design work; its file type is .WDS. The WRITE WDS application may
be used to save current workspace data in a WDS file. Conversely,
READ WDS may be used to retrieve the information in a WDS file for
_________ ___________ _______ ____
further work. See also Workspace, Environment, and Archive Data
_________
Structure.
workspace:
workspace: A temporary area of computer memory or a file named
WORKSPACE.VLS that contains the description of a printed-wiring
board.
While using VLS, all changes you make to a design are stored in the
workspace, a temporary area of computer memory. When you exit the
VLS Main Menu, the data in the workspace is automatically saved in
the file named WORKSPACE.VLS and the temporary area of memory is
deleted. When you again enter VLS, the WORKSPACE.VLS file is
automatically read into memory so you can continue work with the
design. You can also use the WRITE WDS application to save the
27
Glossary
Glossary
_______ ____
information in the workspace in a WDS file. See also Working Data
_________
Structure.
WORLD:
WORLD: A set of software and data elements used to run VLS. See
___________
Environment for a list of these elements.
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