| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 9.2 | AGENT: A VLSI ARCHITECT'S ASSISTANT | DELNI::ROUNDS | | Thu Nov 12 1987 12:37 | 54 |
| From: TWOCAD::SPICE::TSS "22-Oct-1986 1655" 22-OCT-1986 21:01
To: TSS Distribution
Subj: Hudson TSS - Drongowski - Wed. Nov. 5 - 10:00 - HWM
TITLE: "AGENT: A VLSI Architect's Assistant"
SPEAKER: Paul J. Drongowski - Case Western Reserve University
As design problems and VLSI systems grow in size and complexity, they
become particularly sensitive to communication delays. Long wires may
erode any potential increases in speed through a reduction in scale.
For centralized synchronous control systems, the problem is
particularly severe as the longest global wire in a chip design
carries the signal with the most important temporal function - the
clock. Additional delays are incurred in multiple chip systems where
key functions may reside in two or more different packages that are
interconnected at the board or backplane levels. Tools and techniques
are needed to properly partition a design across multiple chip
boundaries (reducing off-chip delays) and across the surface of a
single die (reducing long wire delay). At the architectural level,
the partitioning process is as much algorithmic (behavior plus
structure) as it is physical. Further, all three decision domains
interact.
A Graphical Design Language, Gdl, has been developed that captures a
design specification in the behavioral, structural and physical
domains. Principles and techniques are being devised to guide and
assist the partition of a design expressed in this language. The
principles will be codified in executable rules which will form the
knowledge base of a designer's assistant, AGENT. This is a team effort
supported by the Semiconductor Research Corporation under contract
85-02-057.
Paul Drongowski received his Ph.D. degree from the University of Utah
in 1982. Dr. Drongowski is the first Jennings Distinguished Assistant
Professor of Computer Engineering and Science at Case Western Reserve
University and is Associate Director of its Automation and Intelligent
Systems Research Center. Dr. Drongowski's work concentrates on
descriptive methods to partition a VLSI System at a high level of
abstraction such that a satisfactory mixture of speed, space and power
characteristics may ultimately be attained. The foundations of this
approach are described in his book "A Graphical Engineering Aid for
VLSI Design", UMI Research Press, 1985."
DATE: Wednesday, November 5, 1986
TIME: 10:00
PLACE: Hall of White Mist, HLO1 - Hudson, MA.
HOST: Sudhir Kadkade, SW Engineer - CAD/DECSIM
|
| 9.3 | DATA PATH LAYOUT GENERATION SYSTEM | DELNI::ROUNDS | | Thu Nov 12 1987 12:37 | 43 |
| From: TWOCAD::SPICE::TSS "03-Nov-1986 1626" 3-NOV-1986 20:49
To: TSS Distribution
Subj: HUDSON TSS - TRICK - TUESDAY, NOV. 18 - 10:00 - HWM
TITLE: "Data Path Layout Generation System"
SPEAKER: Mike Trick - CMU
Much of the design automation effort at CMU has been focused on
the synthesis of a structural description of a digital circuit from
a behavioral description of that circuit. To do complete design
automation, there is a need for a tool that will automatically
generate a physical realization of a circuit from the structural
description. Towards this end, we propose a system that partitions
the structural specification of the circuit into groups of modules
that can be implemented efficiently by placing the modules in a
row. The rows of modules are placed so as to minimize the length
of the interconnections and the number of tracks needed to make the
connections. Parameterized procedures written in C generate the
modules and data path clusters.
Michael T. Trick received his B.S. in Computer Engineering from the
University of Illinois in 1982. He is currently a Ph.D. Candidate
at Carnegie-Mellon University and expects to complete his
requirements in the Fall of 1987. Mike Trick was a DEC Fellow from
Sept. '85 - Sept. '86. He received an SRC fellowship for the '86 -
'87 year. Mr. Trick's current project is titled "Automatic
Synthesis of Data Path Layout".
DATE: Tuesday, November 18, 1986
TIME: 10:00 a.m.
PLACE: Hall of White Mist, HLO1 - Hudson, MA.
HOST: Dick Davis, Semi-Custom Mgr. - CAD
|
| 9.4 | MOSFET CHARACTERIZATION | DELNI::ROUNDS | | Thu Nov 12 1987 12:38 | 44 |
| From: TWOCAD::SPICE::TSS "24-Dec-1986 0919" 24-DEC-1986 14:14
To: TSS Distribution
Subj: HUDSON TSS - PING KO - THURSDAY, JAN. 15 - 10:00 - HWM
TITLE: "MOSFET Characterization and Modeling for Circuit
Simulation"
SPEAKER: Ping Ko, Berkeley
It is extremely difficult to construct a thorough and accurate analytical
model for MOSFET - convenient or LDD - that represents all aspects of the
device physics and yet is computation-efficient. As a result, MOSFET
models for circuit simulation have become increasingly semi-empirical. A
natural consequence of this trend is that the hardware, algorithms, and
software for extracting the model parameters are now vital parts of a
model.
This talk will describe the ongoing device modeling efforts at Berkeley,
to support SPICE, in particular the BSIM (Berkeley Short-channel IGFET
Model) project. A brief overview of the research facilities at Berkeley
and the current status of the BSIM project will be given first. The rest
of the talk will concentrate on the modeling and characterization of
intrinsic device capacitances and hot-electron effects.
Ping K. Ko received his Ph.D. degree in Electrical Engineering in 1982
from the University of California at Berkeley. His thesis work concerned
hot-electron effects in short-channel MOSFETs. Dr. Ko spent two years,
1982 and 1983, at Bell labs,Holmdel, working on high-speed MOS technol-
ogies. Since January 1984 he has been with the EECS Department of the
University of California at Berkeley where he is now an associate
professor. His current research interest is in the high-speed integrated-
circuit technologies and devices, and in device modeling for circuit
simulation.
DATE: Thursday, January 15, 1987
TIME: 10:00 am
PLACE: Hall of White Mist, HLO1 - Hudson, MA.
HOST: Narain Arora, Principal Engineer - Process/Device Simulation
Group
|
| 9.5 | APPLICATIONS OF TRANSMISSION MICROSCOPY | DELNI::ROUNDS | | Thu Nov 12 1987 12:39 | 53 |
| From: TWOCAD::SHARE::TSS "22-Jan-1987 1319" 22-JAN-1987 18:08
To: TSS Distribution
Subj: Hudson TSS - Jamie Rose - Tuesday, February 24 - *2:00 pm - HWM
TITLE: "Applications of Transmission Electron Microscopy in Wafer
Fabrication, LSI Development, and Finished Devices"
SPEAKER: Jamie Rose, DEC
Transmission Electron Microscopy (TEM) is a powerful tool supporting
materials research, development, and failure analysis in the fields of
ceramics, metals, and semiconductors. The special strength of TEM lies
in its ability to provide structural and spectroscopic information at
or near the atomic level. Hence it has proven very useful in cross
sectional observations of thin films and LSI devices. The latest gen-
eration of all-purpose analytical TEM's (such as the JEOL 2000FX at
Northboro) optimizes the combination of high-resolution TEM imaging and
microanalytical capabilities: lattice imaging of 2.8A is possible along
with fine-probe analysis of areas down to 20A across, utilizing electron
diffraction and x-ray dispersive and energy loss spectroscopies. Since
very thin samples are employed, the beam broadening limitations of SEM
work are largely avoided. Examples of work performed at Northboro and
elsewhere serve to illustrate potential applications of this technique,
with emphasis given to thin-films on silicon wafers and LSI related
structures. Examples to be discussed include; - phosphorus segregation
at grain boundaries in polysilicon
- the atomic structure of silicon grain boundaries
- structure of the silicon/silicon dioxide interface
- grain structure and film thickness of various thin films
- cross sectional studies of hard disc magnetic media
- cross sectional examination of silicon based devices
- contacts to gallium arsenide
- surface roughness via replication
In these studies, TEM provided film thickness measurements accurate to a
few angstroms, defect and phase identification and morphology, and tests
of defect atomic models.
Jamie Rose received a A.B. degree in Physics from Brandeis University
and a M.S. and Ph.D. (1985) in Materials Science from the University of
California at Berkeley where he worked on applications of Transmission
Electron Microscopy to the study of defects in silicon. He worked as a
staff scientist at Lawrence Berkeley Laboratory until joining Digital's
Material & Technology Analysis Laboratory in 1986.
DATE: Tuesday, February 24, 1987
TIME: *2:00 p.m.
PLACE: Hall of White Mist, HLO1 - Hudson, MA.
HOST: Rich Schuman, Manager of Semiconductor Development
|
| 9.7 | DESIGN OF ANALOG MOS CIRCUITS | DELNI::ROUNDS | | Thu Nov 12 1987 12:40 | 111 |
| From: TWOCAD::SHARE::TSS "03-Feb-1987 1110" 3-FEB-1987 21:41
To: TSS Distribution
Subj: design of analog MOS integrated circuits course
LSI
ENGINEERING TRAINING AND EDUCATION
ANNOUNCES
Design of Analog MOS Integrated Circuits
March 23 - 27, 1987
VLSI Training Room, HLO2-1
Hae-Seung Lee, Charles Sodini, MIT
COURSE DESCRIPTION:
In this program, device properties and electrical models for
both active devices and passive devices will first be discussed
to provide basic understanding of MOS technologies. Building
blocks such as operational amplifiers and voltage comparators
will then be discussed. Design considerations, engineering
tradeoffs and various design approaches will be presented.
Finally, analog subsystems including MOS bandgap references,
A/D and D/A converters, and switch capacitor filters will be
discussed.
Required background: Basic knowledge in semiconductor devices
and circuits is necessary. An entry-level understanding of
statistics is also assumed.
At the end of this course, one should be able to design various
analog circuits and subsystems with a state-of-the-art CMOS VLSI
process. One should have developed a good understanding of the
inter-relationship of device processing, device physics, and
techniques of analog circuit design.
Class size is limited to 20.
FEE: $950
HUDSON TECHNICAL TRAINING COURSE REGISTRATION FORM
COURSE TITLE : Design of Analog MOS IC Course
DATES : March 23 - 27, 1987
COST : $950
Please return completed form to: ET&E REGISTRAR
HLO2-2/N09
For more information, contact Karin Aslanian, DTN 225-5706
or, SHARE::ASLANIAN.
Name:___________________________ ENET Address:________________
Badge #:________________________ DTN:_________________________
LOC/MS:_________________________ Organization:________________
Cost Center:_______ Manager's Signature_________________________
To help us profile the participants of this course, to evaluate it,
and to plan future courses please answer the following questions with
your manager.
(Circle the letter that most accurately describes your response)
1. Why are you taking this particular course?
A. Requirements of my current job immediately or within six months.
B. It fits into my technical development plan.
C. I anticipate moving to a job where this course will be useful.
D. While not directly related to my primary responsibilities, it
will help me with some parts of my job.
E. This is a subject I am interested in.
F. My manager has requested me to take it.
2. Do you expect this course to make a specific difference in your
ability to do your job?
A. Yes, definitely.
B. Probably.
C. Maybe.
D. Probably not.
E. No.
3. What is your last degree?___________ The year?____________
4. Describe the specific results you expect from taking this course.
|
| 9.8 | FRAMEWORK OF KNOWLEDGEBASED CIRCUIT SYNTHESIS | DELNI::ROUNDS | | Thu Nov 12 1987 12:41 | 47 |
| From: NACAD::SHARE::TSS "21-Apr-1987 0821" 21-APR-1987 13:41
To: TSS Distribution
Subj: HUDSON TSS - RICK CARLEY, CMU
****************************************************************************
UNANNOUNCED SEMINAR
****************************************************************************
TITLE: "A Framework for Knowledge-Based Analog Circuit Synthesis"
SPEAKER: Rick Carley, CMU
A framework for knowledge-based analog circuit design tool will be
described. Analog circuit topologies are represented as a hierarchy
of connected functional blocks in which the lowest level of blocks are
individual devices, including their type, width, and length.
Implementation of a design style selector that selects the topology most
appropriate for the current task and a planning mechanism that
translates performancec specifications between levels in this circuit
hierarchy will be discussed. Although "knowledge-based" has come to be
synonymous with "rule-based" in most CAD applications, the use of the
planning mechanisms that rely primarily on algorithmic steps rather than
on rule execution will be advocated. A prototype operation amplifier
design tool that generates sized transistor schematics for several styles
of CMOS operational amplifiers from performance specifications and
process parameters has been built. SPICE simulations of the design will
be compared with the operational amplifier design specifications.
Rick Carley received the S.B., S.M., and Ph.D. degrees in Electrical
Engineering from the Massachusetts Institute of Technology. In 1976, 1978,
and 1984 respectively. During the summers of 1979, 1980, and 1981,
he worked for MIT's Lincoln Laboratories. In 1984, he joined Carnegie
Mellon University, Pittsburgh, PA, as an Assistant Professor of
Electrical and Computer Engineering. His research is in the area of
synthesis, analysis, and simulation of systems that combine analog
and digital elements. He received a National Science Foundation
Presidential Young Invesitgator Award in 1985.
DATE: Monday, May 4, 1987
TIME: 2:00 p.m.
PLACE: Hall of White Mist, HLO1 - Hudson, MA
HOST: Wayne Shumaker, Principal Engineer, Analog/Mass Storage
Group - SEG
|
| 9.9 | LYNX WORKSTATIONS | DELNI::ROUNDS | | Thu Nov 12 1987 12:42 | 76 |
| From: TWOCAD::MILRAT::COTOIA "14-Jan-1987 1028" 14-JAN-1987 13:50
To: @INTEREST.DIS
Subj: MAET TSS - Lynx Technical Overview - JANUARY 27 at 2:00 PM
****************************************************************
M. A. E. T. T E C H N I C A L S E M I N A R S E R I E S
****************************************************************
TOPIC: Lynx Technical Overview
SPEAKER: Branko J. Gerovac, High Performance Workstations
TECHNICAL HOST: Gil Steil, Group Manager,
High Performance Workstations
January 27, 1987
2:00 - 4:00 PM
Mill Cafeteria Conf. Rm. (MLO5-4)
NO REGISTRATION REQUIRED
ABSTRACT:
Lynx is a high performance interactive 3-D graphics workstation
for engineers and scientists working in mechanical design,
molecular modeling, and other areas of graphical modeling and
interaction. Lynx is a joint engineering project with Evans and
Sutherland Corp., and is designed to be consistent with the
emerging DECwindows strategy and to be a fully cooperating member
of Digital's worksystem family.
Lynx incorporates extensive support for 3-D graphics, bitmap
graphics, and windowing. It provides several unique features
which are atypical of high performance 3-D graphics workstations:
(1) realtime dynamic rendering of 3-D graphics at five times
higher throughput than workstations built with existing
technology, (2) full performance antialiasing and depth cuing
offering up to eight times higher image quality, (3) complete
device coordinate bitmap graphics to support general workstation
software environments and applications, and (4) hardware support
for windowing and graphics contexts to enable full performance
dynamics in occluded windows with separate color mapping and
double buffer mechanisms.
The presentation describes the hardware and software organization
of Lynx and discusses key components and algorithms.
SPEAKER:
Branko Gerovac is a principal engineer with the High Performance
Workstations Group, and has worked on Lynx since its inception 20
months ago. In 5 years with Digital, he has worked on
workstation projects covering graphics, windowing, human
interfaces, and hardware organization. For 10 years prior to
joining Digital, he was a research associate with a learning
theory research laboratory where he led development of research
hardware and software including video and film, introduced
personal computing, and contributed to fundamental research. He
holds a BA in Physics from Brandeis University.
_________________________________________________________________
REMINDER: If you miss one of our live presentations, most MAET
seminars are videotaped (3/4" and 1/2" format) for later viewing.
These tapes are circulated through the Mill Library. Reserves
may be placed by contacting your nearest site library with the
title and speaker. NOTE: Tapes are catalogued and ready for
first circulation approximately six weeks after the seminar date.
*****************************************************************
MAYNARD AREA ENGINEERING TRAINING is a part of LEST's
DESIGN AND PROCESS ENGINEERING
*****************************************************************
|
| 9.10 | MLO/HLO TRAINING CONTACTS | DELNI::ROUNDS | | Thu Nov 12 1987 14:31 | 6 |
|
MAYNARD AREA ENGINEERING TRAINING - MILRAT::COTOIA
(LEST DESIGN AND PROCESS ENGINEERING)
TECHNICAL SEMINAR SERIES - SHARE::TSS
(HUDSON ENGINEERING TRAINING AND EDUCATION - HLO2-2/N09)
|
| 9.13 | HOW TO REQUEST AI TSS PAMPHLET | DELNI::ROUNDS | | Mon Dec 14 1987 16:34 | 39 |
|
From: ISTG::TSS "11-Dec-1987 1151" 11-DEC-1987 17:57
To: TSS Distribution,TSS
Subj: If you wish hardcopy AI TSS updates, send badge number to ISTG::TSS
Most of you currently receive a copy of "Interconnects", which is a pamphlet
of upcoming Technical Seminars and Courses offered by ETE (Hudson Engineering,
Training and Education).
In February, the AI Technical Seminar Series, located at DLB5 (Donald Lynch
Blvd, Marlboro, MA), will start to publish its own phamplet, listing a calendar
of scheduled, upcoming AI Technical Seminars to be offered at DLB5 cafeteria.
If you wish to receive the AI TSS phamphlet,
PLEASE, SEND YOUR BADGE # TO ISTG::TSS.
AI TSS is now using a new mail list facility, and our distribution list
needs to be recreated, as it cannot be transferred.
This new facility will allow us to always have your current mailstop for hard
copy mailing. If you send your Digital mailstop to ISTG::TSS, you should not
have to worry about continuing to receive your AI Technical Seminar Series
calendars for up-coming AI seminars.
NOTE:
+-----------------------------------------------------------------------+
| If you wish to continue to receive the latest announcements via ENET, |
| however, we will still need to be kept up-to-date on any NODE NAME |
| changes, as we have in the past. |
+-----------------------------------------------------------------------+
Please do this NOW, before you forget!
---> Send your Badge # to ISTG::TSS <--- for hard copy distribution.
Thank you for your continued support and interest in AI TSS.
Jude Partridge, AI TSS Specialist
|
| 9.14 | BIPOLAR COURSE - HLO | DELNI::ROUNDS | | Fri Dec 18 1987 06:45 | 74 |
|
From: NACAD::SHARE::TSS "HUDSON ET&E 225-5272 17-Dec-1987 1658" 18-DEC-1987 02:06
To: TSS Distribution
Subj: BIPOLAR TECHNOLOGY COURSE...INSTRUCTORS
BIPOLAR TECHNOLOGY
INSTRUCTORS: Drs. Charles Sodini & Stephen Senturia, MIT
DATES: 6-7-8-25-26 JANUARY, 1988
This course is intended to help the practicing engineer understand the
connection between semiconductor device physics and actual device models
for p-n juction and bi-polar transisitor devices. An advanced and highly
theoretical course, "Bipolar Technolgy" prerequisites are; an advanced
understanding of solid-state physics, a thorough knowledge of semiconductor
processing, and familiaity with much of the course material covered in the
cirruculum model.
Semiconductor band and bond models
Thermal equilibrium; Fermi level
P-N junction electrostatics in equilibrium;
quasi-neutrality; depletion approximation; Debye lenght
Reverse bias junction; junction capacitance; breakdown
Continuity equation; generation recombination; excess carriers
P-N Junction I-V charateristic
Space charge region currents; charge storage; diode transients
Schottky and hererojunction diodes
Bipolar transistor action; active bias; uniform and no-uniform doping
Ebers-Moll and Gummel Poon quasi-static models
Space-charge recombination; early effect; high-level injection;
base spreading resistance; Kirk effect
Base transit time; large signal charge-control models
Small-signal charge-control models
Measurement of SPICE parameters
Place: Mt. Washington Conference Room, HLO1-1
Cost: $1050.00
To register online, set host to share, username=courses
password=courses. For more information contact Mary Ayres
at 225-5221, or, at SHARE::AYRES.
|
| 9.15 | Computer Aided Circuit Simulation course | DELNI::ROUNDS | | Mon Jan 18 1988 08:43 | 103 |
| From: NACAD::SHARE::TSS "HUDSON ET&E 225-5272 15-Jan-1988 1426" 15-JAN-1988 23:12
To: TSS Distribution
Subj: Circuit Simulation Course
SCO ENGINEERING TRAINING AND EDUCATION
ANNOUNCES:
"COMPUTER-AIDED SIMULATION OF INTEGRATED CIRCUITS"
Prof. Alberto L. Sangiovanni-Vincentelli
Department of Electrical Engineering and Computer Science
University of California at Berkeley
February 8-12, 1988
Mt. Washington Conference Room, HLO2-1
The course will cover the following topics:
"First day"
Introduction and description of the course.
Formulation of the circuit equations: Nodal Analysis,
Sparse Tableau and Modified Nodal Analysis.
Methods for the solution of linear circuits:
sparse matrices. Accuracy and sparsity.
Pivoting methods.
"Second day"
Methods for the DC analysis of nonlinear circuits.
Newton-Raphson and its modifications.
Convergence properties. Continuation Methods.
Methods for the transient analysis of nonlinear circuits.
Linear multistep methods.
"Third day"
Order of integration methods and local truncation error.
Stability. Stiff stability and Gear's methods.
Building a circuit simulator:
SPICE architecture.
"Fourth day"
Frequency domain analysis for nonlinear circuits.
Finite difference methods, shooting methods.
Harmonic balance techniques.
Harmonic Newton methods:
Harmonica.
"Fifth day"
Computer-Aided Simulation of VLSI circuits:
Block LU decomposition and Tearing methods.
Relaxation based electrical simulation:
Gauss-Seidel-Newton methods and Iterated Timing Analysis.
Event driven simulation.
Waveform Relaxation. Convergence properties.
The partitioning problem: Static and Dynamic partitioning.
Parallel algorithms and their implementation
on multi-processors.
There is no text that covers the entire spectrum of
this course.
A reader with a set of papers that will be covered in class
will be made available.
The book "Relaxation Techniques for the Simulation
of VLSI Circuits" by J. White and A. Sangiovanni-Vincentelli
Kluwer Academic Publishing Co.,
will be useful.
While not required, this book covers several of the topics
we will discuss in class and hence its reading
recommended.
COURSE FEE: $1050
Registration for this class can be completed by utilizing Engineering
Training's On-Line registration system. To access the "Courses" facility,
set host to SHARE. Username = COURSES, PASSWORD = COURSES. Registration
process is menu driven.
|
| 9.16 | MAET Physical Relocation | DELNI::ROUNDS | | Mon Jan 18 1988 08:43 | 40 |
| From: NACAD::MILRAT::MCALLISTER "Terri 223-6602 MLO4-5/U69 Maynard Area Eng Trng 15-Jan-1988 1608" 15-JAN-1988 22:47
To: @DISTRIBUTION,MCALLISTER
Subj: Maynard Area Engineering Training
____________________________________
| | | | | | | |
| d | i | g | i | t | a | l | INTEROFFICE MEMORANDUM
|____|____|____|____|____|____|____|
TO: @Distribution DATE: January 15, 1988
FROM: Theresa McAllister
DEPT: Maynard Area Eng Training
EXT: 223-6602
LOC: MLO4-5/U69
ENET: MILRAT::MCALLISTER
SUBJECT: Maynard Area Engineering Training
As of January 26, 1988, the Maynard Area Engineering Training Group
will move from MLO4-5 to MLO1-3.
Our new mailstop will be MLO1-3/U69
Following are the pole locations:
Laurie Dumont MLO1-3/pole 35A
Paula Coleman MLO1-3/pole 36B
John Hamer MLO1-3/pole 33B
Sally Light MLO1-3/pole 34A
Theresa McAllister MLO1-3/pole 35B
Gereda Pruitt MLO1-3/pole 34A
Nick Ugrinow MLO1-3/pole 36A
Linda Watson-West MLO1-3/pole 33A
|
| 9.17 | ABC's of CHIP MANUFACTURING | DELNI::ROUNDS | | Fri Jan 22 1988 10:19 | 50 |
| From: NACAD::SHARE::TSS "HUDSON ET&E 225-5272 21-Jan-1988 1513" 21-JAN-1988 22:46
To: TSS Distribution
Subj: ABC's of CHIP MANUFACTURING
SCO ENGINEERING TRAINING AND EDUCATION
ANNOUNCES:
"ABC's OF CHIP MANUFACTURING"
(A one day tutorial)
FRIDAY, JANUARY 29th, 1988
8:00 AM - 5:00 PM
HALL OF WHITE MIST CONFERENCE ROOM, HLO1-1
INSTRUCTOR: STEVE MITTLEMAN, Ph.D.
This one-day program assumes no prior knowledge of semiconductor
manufacturing process and introduces students to the science. The
program is geared to high-school level educational backgrounds and
will be limited to the first twenty registrations. Students will
be exposed to all of the fundamental terms and processes associated
with chip manufacturing. This program is recommended for members
of non-technical support staffs, administrative personnel, and in-
dividuals interested in simple explanations of particular processes.
Topics to be covered include the manufacture of silicon, photolitho-
graphic processes, oxidation, deposition, etching, metallization,
probe, passivation, and test.
Steve Mittleman teaches at Northeastern University and is employed at
Hanscom Field.
Course Fee: $200
To register please access our On-Line registration facility by setting
host to node SHARE, Username = Courses, Password = Courses. Registra-
tion is completely menu driven.
For information please contact Mary Ayers at 225-4071, or, at SHARE::AYRES
|
| 9.18 | STANFORD TECH DIGEST | DELNI::ROUNDS | | Mon Apr 11 1988 09:30 | 568 |
| From: CALDEC::ABRAMS "Only Visiting This Planet 04-Apr-1988 1718" 5-APR-1988 01:19
To: @STD,ABRAMS
Subj: Stanford Technology Digest Vol 1 No 9
*******************************************************************************
***** STANFORD TECHNOLOGY DIGEST *****
**** VOLUME 1 NUMBER 9 ****
*** MARCH 1988 ***
** Reesa Abrams, Ira Machefsky Editors **
*******************************************************************************
STANFORD TECHNOLOGY DIGEST is a monthly technology transfer forum for
communicating research, technical, and competitive information between
the Digital and Stanford University communities.
*******************************************************************************
The purpose of STD is to inform Digital readers of events and activities of
interest in the Stanford research community. The style of this digest will
be to provide abstracts or short articles of interest with references to
more detailed information for you to pursue should you wish to follow-up.
This magazine is restricted for use only by employees of Digital Equipment
Corporation.
We welcome contributions from anyone who is sponsoring research, doing
work or just visiting Stanford at any time.
We also encourage comments from readers and Letters to the Editor, which
will be published with the author's permission.
If you wish to subscribe to STD or change your subscription address
please send mail to CALDEC::ABRAMS.
*************************************************************************
*************************************************************************
TABLE OF CONTENTS
THIS ISSUE 10 PAGES
I. MANUFACTURING IN THE 90'S - STANFORD BUSINESS SCHOOL
II. BAY AREA SYSTEMS SEMINAR
III. ME210 DESIGN REVIEW OPPORTUNITY
IV. SEMINARS AT BERKELEY
V. THE MANAGERIAL CHALLENGES OF INTEGRATING CAD/CAD
VI. INFORMATION NEEDED FOR JOINT DEC/APPLE UNIVERSITY PROGRAM
VII. DEC PERSONNEL ON CAMPUS
*******************************************************************************
*******************************************************************************
I. MANUFACTURING IN THE 90'S - STANFORD BUSINESS SCHOOL
On Saturday, April 16, 1988 the Stanford Graduate School of Business will
run a one day conference to address the major issues facing the manufacturing
sector.
"Increasing competition, accelerating change, globalizing industries, uncertain
government policy ... today's business environment grows ever more complex.
As companies strive to win, manufacturing is emerging as a critical strategic
resource. Excellence demands that manufacturing integrate with all other
parts of the organization to produce a coherent winning strategy. JIT,
zero defects, flexible manufacturing are typical of manufacturing issues
profoundly affecting all aspects of a company's operations. For the
manufacturing industry of the 90's success is truly on the line."
Keynote speakers: Our Time Has Come - A Manufacturing Renaissance
George Fisher, President and CEO, Motorola
Competing in the Global Marketplace
Shoichiro Irimajiri, President, Honda of America
Manufacturing
Workshop Leaders:
A1. A Case for CIM
J. Tracey O'Rourke, President and CEO, Allen-Bradley
A2. Distributed Technologies in High Tech Manufacturing
Dr. Mihir PArikh, President and CEO, Asyst Tech. Inc.
A3. Innovative Strategies in Small Scale Manufacturing
Maurice E.P. Gunderson, President, Edison Systems Corp.
A4. Managing Major Transitions in Manufacturing
Homer Moeller, Senior V.P. Operations, Hanes Knit Prod.
A5. Quality, Culture and Renewal in American Manufacturing
Robert Waterman, President, Waterman and Co.
A6. Technology and Global Sourcing
Ralph Russo, V.P. Worldwide Operations, Apple Computer
A7. Tomorrow's Accounting Today
Professor Geo. Foster, Stanford Graduate School
of Business and John Lamley, Group Controller, H.P.
A8.
The Opportunities and Problems of Multi-National
Manufacturing
Robert C. Graham, President, RCG Associates, Inc.
Tom Metz, Program Manager 9370 System Development, IBM
B1.
Benefitting from Japanese Style Management in the U.S.
Eystein Thordadson, Senior V.P. General Manager,
Hillsboro Facility, Fujitsu America
B2. Careers in Manufacturing: Pros, Cons, Paths, and
Salaries
Bill Bridenbaugh, Senior V.P. Boise Cascade
Scott McNealy, President, Sin Micro
B3. Changing the Role of Manufacturing in a Large Corp.
Earl Hewitt, General Manager, Operations, Northern
Telecom
B4. International Sourcing as a Long-Term Strategy
David E. Patterson, V.P. Supply, Cummins Engine
Andrew Chu, Southeast Asia Business Director, Cummins
Engine
B5. Manufacturing as a Competitive Advantage
Elizabeth Haas, Principal, McKinsey & Co.
B6. Manufacturing Strategy - An Example That Worked
Jean-Pierre PAtkay, General Manager
Manufacturing Productivity Division, H. P.
Measuring Quality in the Plant and in the Eyes of the
B7. Customer
Doug Campbell, CEO, Kilovac
Martin Dorio, Dir of Quality and Productivity, FMC
B8. New Product Development/Manufcturing Start-Up
Walt Rosenbrough, Senior V.P. Marketing,
SSI/Hillenbrand Ind. and Prof. Steven Wheelwright
Stanford Graduate School of Business
B9. Plant Development:Innovation in Operations
Mark Chestnut, V.P. Operational Effectiveness,
Cummins Engine
Biotechnology Startups: Shooting For Wild Success
C1. Gary T. Steele, President and CEO, Molecular Devices
Encouraging Innovation at 3M: Organizational
C2. and Cultural Mechanisms
Bill DeGenaro, Director of Innovation Resources, 3M
C3. Optimizing the Location of Business Operations
Tsuyoshi Kawanishi, Senior V.P. Semi-Conductor
Group, Toshiba Corporation
C4. Overview of Quality Engineering For Product Design:
Case Studies of the Taguchi Method
Dr. Genichi Taguchi, Executive Director, American
Supplier Institute and Yuin Wu, V.P. American
Supplier Institute
C5. The Impact of Changing Technology on the workforce
Austin E. Vanchieri, President, Information
Systems Division, Xerox Corp.
The Role of Manufacturing in U.S. International
C6 Competitiveness
Allen J. Lenz, Director, Office of Trade and Investment
Analysis, U. S. Dept. of Commerce
C7. Time-Based Competition
George Stalk, V.P. Boston Consulting Group
Transferring New Products to Manufacturing:
C8. Too Soon or Too Late
Thomas Huseby, V.P. Industrial, Raychem
To Register contact:
The Manufacturing Conference
Graduate School of Business
Stanford, University
Registration Fee:
Students $12
Corporate Prepaid $125
Day of the Conference $150
Lunch and Reception Included
INDICATE CHOICE PREFERENCE FOR EACH OF A, B, AND C CONFERENCES.
Capacity is limited and priority will be given to registrations prior
to April 1. For more information please call 415 - 493 - 9097.
If you are going to attend please inform Reesa (CALDEC::) Abrams so we
can assure the maximum Digital coverage for this seminar.
*******************************************************************************
II.
BAY AREA SYSTEMS SEMINAR
The Bay Area Systems Seminar was held at Stanford University
on Friday, March 25th. The abstracts of the program follow.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Concurrent, Real-time Collection on Stock Multiprocessors
John R. Ellis, Kai Li, Andrew Appel
DEC-SRC
E-mail: DECSRC::Ellis
We've designed and implemented the first copying garbage-collection
algorithm that is efficient, real-time, concurrent, runs on commercial
uniprocessors and shared-memory multiprocessors, and requires no change
to compilers. The algorithm uses standard virtual-memory hardware to
detect references to "from space" objects and to synchronize the
collector and mutator threads. We've implemented and measured a
prototype for the ML language running on SRC's 5-processor Firefly.
It will be straightforward to merge our techniques with generational
collection (Ungar, Shaw). An incremental, non-concurrent version could
be implemented easily on many versions of Unix.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
The Sun Network Software Environment
Masahiro Honda
Sun Microsystems
The Sun Network Software Environment (NSE) is a network-based object
manager for software development. The goals of the NSE are to 1)
facilitate parallel development of large software systems, 2) help
maintain consistency and completeness of objects being developed, and
3) be extensible to different types of objects. Parallel development
is supported through an optimistic concurrency control mechanism, where
developers do not acquire locks before modifying objects. Instead,
developers copy objects, modify the copies, and merge the modified
objects with the originals. The NSE provides copy operations on units
that are complete and consistent sets of objects. These copy
operations produce logical copies; a physical copy of and object is not
made until the object has been modified. To help developers merge
objects, the NSE detects conflicting modifications and provides tools
to resolve the conflicts. Finally, the objects managed by the NSE are
typed, and the set of types is extensible by tool builders. Objects
manipulated by different software tools can be managed by the NSE by
tool builders defining NSE types for these objects.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Spider: High-Performance Processor Interconnect Software
Kent Treiber
IBM Almaden Research Center
Spider is a completed research project on high performance
processor interconnect software. The original goal was to
support message transfer between closely coupled
mainframes with roughly an order of magnitude
fewer instructions than currently available software
without inventing new architectures.
It's interesting to note that Spider was implemented
on top of what some view as an archaic, monsterous
and slow operating system: MVS. The talk will include an
overview of Spider, discuss some of the interesting design
issues and review performance data.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
The Analysis of Diskless Workstation Traffic on an Ethernet
Riccardo Gusella
University of California, Berkeley
E-mail: [email protected]
We analyze the traffic on a 10 Mb/s Ethernet local area network
that connects diskless workstations to file servers in a university
environment. The traffic is substantially heavier than has been recorded
in previous studies; over 1-second intervals it frequently exceeds
30% of the network bandwidth.
We display and interpret the distribution of packet lengths and packet
interarrival times for the three protocols that carry significant traffic:
TCP (character traffic), ND (paging traffic), and NFS (remote file
access traffic). The two latter protocols account for 68% of
the packets and 94% of the data bytes on the network.
File access to a remote file server generates bursts of traffic
that can last several seconds and demand bandwidths in the order
of 120K bytes per second, or about 10% of the Ethernet bandwidth.
*******************************************************************************
III.
YOU ARE INVITED
to a
D E S I G N R E V I E W
of the
Stanford University ME210 Design Project
"AUTOMATIC TILT ADJUSTING ROBOT END EFFECTOR"
Your comments on the design would be greatly appreciated!
If you know anyone else who might be interested, please
forward this invitation.
When: Thursday April 7 at 9am
Where: Chelmsford (CTS) Harvard Conference Room
Any Questions: Call Cindy Pribble at dtn 287-3526
++++++++++++++++++++++++++++++++++++++++++++++++++++++
STATUS - Stanford University ME210 Design Project -
"Tilt Adjusting Robot End Effector"
A design team at Stanford University is developing a robot end
effector for placement of components with parallelism problems. A
design review of the project was held at Stanford in early March.
A prototype has been built of the passive tilt design, which features
a ball-and-socket joint to adjust for components in which the grip
surface (usually top of the heat sink) is not parallel to the lead
plane. The joint pivots freely on an air bearing and is supported by
the Bernoulli effect.
Primary objectives of the design are to adjust for tilt, maintain X-Y
placement accuracy, control placement force, and prevent lead damage.
The basic concepts used in their design work seem to work; however,
initial trials with the prototype reveal some problems which must be
corrected. The pneumatic line for vacuum pick-up of the part was
routed through the center of the joint, but this interferes with the
air flow required for Bernoulli effect and the line will have to be
routed around the outside. Other areas of concern include bearing
alignment in the z-compliant device, and the transition from a
frictionless air bearing to a rigid joint.
Using this gripper results in a placement sequence as follows:
- Pick up chip from carrier
- Place chip on level surface
- Adjust for tilt with air bearing
- Lock joint and pick up chip
- Look at chip and make X-Y offset calculation
- Place chip on board, with lead plane parallel to board surface.
Future plans for the design team include completion of the acceptance
test procedure, further debugging of the prototype hardware, and
set-up of a work station utilizing the AdeptOne robot for thorough
demonstration and testing of the prototype. The design project is
scheduled for completion in June, 1988.
*******************************************************************************
IV. SEMINARS AT BERKELEY
We are sometimes asked for a list of the research interests of faculty
members at different universities. The following list of the CS
seminars given at Berkeley shows the faculty sponsors and their research
areas.
I. MAJOR SEMINARS
These seminars will be held every semester.
CS 298-1 Computer Systems [Hardware]
Anderson, Despain, Ferrari, Katz, Ousterhout, Patterson
CS 298-2 Theoretical Computer Science
Blum, Canny, Karp, Lawler, Seidel, Vazirani
CS 298-3 Software Systems
Fateman, Ferrari, Graham, Harrison, Hilfinger, Kahan, Rowe,
Stonebraker, Wilensky
CS 298-4 GRA-VIS-MOD [Graphics, Vision, Geometric Modeling]
Barsky, Malik, Sastry, Sequin
II. OTHER SEMINARS OFFERED EACH TERM
These are seminars with more than one sponsor. They
are likely to keep going, without regard to faculty sabbaticals
and leaves.
CS 298-6 Symbolic Mathematics and Scientific Software
Fateman, Kahan, Parlett
CS 298-8 Distributed System Performance
Anderson, Ferrari, Smith
CS 298-10 Expert and Knowledge-Based Systems
Russell, Zadeh
CS 298-12 Data Base Design
Rowe, Stonebraker
CS 298-14 Computational Complexity
This seminar is run by and for the grad students in theoretical
CS; faculty are explicitly /not/ invited to attend.
III. SEMINARS SPONSORED BY INDIVIDUALS
These seminars are sponsored by individual faculty members,
primarily as a device for meeting with students they supervise.
These seminars will most likely be scheduled each term, so long
as the faculty sponsor does not go on leave.
CS 298-5 Object Oriented Programming Systems
Rowe
CS 298-9 Postgres Development Issues
Stonebraker
Cs 298-13 Natural Languages
Wilensky
CS 298-18 Language Implementation and Environments Research Group
Graham
CS 298-28 Software Engineering
Ramamoorthy
IV. PROJECT-ORIENTED SEMINARS
These seminars are tied to specific research projects and presumably
will continue as long as the project does--should check with the
faculty concerned each term or year.
CS 298-19 SPUR
Katz, Ousterhout, Patterson
CS 298-20 Transaction Processing Architectures
Katz, Patterson, Stonebraker
*******************************************************************************
V. THE MANAGERIAL CHALLENGES OF
INTEGRATING CAD/CAM
A new report has been released by Paul Adler of IE Dept. at Stanford (also
a part of SIMA) in February 1988. It summarizes the results of an investigation
into the managerial challenges of integrating CAD and CAM. It was guided by
two research questions:
a. What are the organizational conditions and managerial approaches
that can maximize the effectiveness of CAD/CAM?
b. What effect is CAD/CAM integration having on the
Design/Manufacturing interface? How should this interface be
managed? Is CAD/CAM the long-awaited solution to persistent
management frustrations and organizational frictions at the
Design/Manufacturing interface?
Nine U.S. electronics businesses and 4 U.S. aircraft companies believed
to be the leaders in CAD/CAM integration were visited. The output is what
is believed to be the 'best practice' in each. Digital was visited.
Three conclusions were reached:
1. There is still struggle to capitalize on CAD/CAM potential.
The integration potential is underexploited.
2. CAD/CAM integration does not solve Design/Manufacturing
problems it highlights them showing organizational and management
issues to be resolved.
3. 5 Key Strategic Challenges to CAD/CAM were identified as
managerial challenges representing skills, procedures, structure,
strategy, and culture.
There is a very comprehensive writeup of about 100 pages with an
executive summary. If you are interested in a copy please contact
Reesa (CALDEC::) Abrams
*******************************************************************************
VI. Information Needed for Joint DEC/Apple University Program
Digital's External Research Program is in the early stages of putting
together a program of joint DEC/Apple projects on university campuses.
These projects are intended to complement/supplement work under way as
internal DEC engineering projects in support of the recent DEC/Apple
announcements. In order to identify areas of interest for this
program we would appreciate hearing from anyone connected with or who
knows about any internal DEC/Apple joint projects. Please send a note
to Ira (RDVAX::) Machefsky. Thanks in advance.
*******************************************************************************
VII. DEC PERSONNEL ON CAMPUS
DEC personnel resident on campus:
Ira Machefsky - CRA Quantum Project Manager
Hewon Hwang - GEEP in Manufacturing Systems Masters Program of SIMA
in ME - Digital return date - 3-21-89
Alex Bronstein - GEEP - finishing a dissertation in Formal
Verification of Concurrent Systems in CS.
Digital return date - 6-30-89
Bruce DeLagi - Co-Director Architecture Project, Heuristic
Programming Project
Reesa Abrams - Technology Transfer Liason
Brian Michon - GEEP MSCS, System Design/Interface - Digital return
date - 4-1-88
Carrie Wilpolt - GEEP MSCS, Software Engineering/Programming Systems -
Digital return date - 4-1-88
Nancy Wogrin - GEEP in AI Masters Program - Digital return date -
7-15-88
********************************************************************************
********************************************************************************
END OF THIS ISSUE
********************************************************************************
********************************************************************************
|
| 9.19 | DIGITAL LOGIC DESIGN COURSE | DELNI::ROUNDS | | Mon Apr 11 1988 09:30 | 114 |
| From: NACAD::SHARE::TSS "HUDSON ET&E 225-5272 08-Apr-1988 1633" 9-APR-1988 00:51
To: TSS Distribution
Subj: DIGITAL LOGIC DESIGN COURSE
COURSE TITLE: Digital Logic Design
DATES & TIMES: May 9th-13th, 1988
8:00 to 8:30 - Arrival, Logistical Details
8:30 - Class begins, runs to 5:00 daily
INSTRUCTOR: John Murray, Oregon State University
PLACE: Mt. Washington Conference Room, HLO2-1
COURSE CONTENT:
This course is intended to introduce the student to the key concepts involved
in going from a word description of a problem to the digital circuit solution.
The major emphasis will be on understanding key concepts. The student
should come out with a solid foundation upon which to build further, rather
than simply certification as a logic designer.
The course will consist of three two-hour lectures plus a laboratory/problem
session each day for five days. The lab session will be devoted to solving
homework problems, which will require the student to carry out a number
of simple designs, reinforcing the lecture material. The laboratory sessions
will be supervised by the course instructors. Lectures will treat the theory
and design of combinational and sequential circuits, design within the
context of the various hardware technologies (MOS, TTL, and ECL), and the
complete solutions to several substantial logic design problems.
Specific topics to be covered include:
1. An integrated view of digital systems, including their evolution,
future trends, digital systems architectural principles, and system
design fundamentals.
2. The information model of digital systems
3. The digital system design process.
4. Datapath design, including the datapath specification process, physical
design considerations, structural issues and timing. Elementary
combinational and sequential logic building blocks for datapaths will
also be covered. In addition, the design of datapath structures such as
decoders, multiplexers, priority encoders, counters, and shift registers
will be discussed.
5. Controller design, including finite state machines, shift register
controllers, and microprogrammed controllers.
6. Memory design and operation, including key memory selection and
application issues.
7. Clocking and timing issues (at each level of the system design
hierarchy)
8. Case studies, including a small computer design, UART, digital signal
processor chip, and a parallel sorting engine.
COURSE OUTLINE:
We breakdown each day into three lectures of 1.5-2 hours each and a
problem session following the third lecture. The instructors are available to
TA the problem sessions.
8:30 to 10:00 Lecture I
10:30 to 11:30 and12:30 to 1:30 Lecture II
2:00 to 5:00 Lecture III and problem session
The week's schedule:
Monday
------
I. Intro/Focus/Overview
II. Basics/Elementary Building Blocks
III. Synthesis of Logic Circuits from Word Specifications
Tuesday
-------
I. NAND/NOR Design
II. Minimization
III. Memory Systems
Wednesday
---------
I. FSM Design
II. FSM Design/Advanced Controller Design (Continued)
III. Timing issues and Examples
Thursday
--------
I. Example: Design of a Sorting Engine
II. Examples: Design of a UART, Design of a Digital Signal Processor
III. Introduction to Silicon Compilation and Other VLSI Technologies
Friday
------
I. All day going over a simple CPU design (Datapath, Microprogrammed
Controller, Microcode, Timing)
========================================================================
Course Fee $1050.00
Please utilize our COURSES registartion program.
. Set host to node SHARE
. Username = COURSES
. Password = COURSES
Program is menu-driven from this point
Course number is 84DLD-01
|
| 9.20 | MANAGER'S INTRO TO VALID | DELNI::ROUNDS | | Mon Apr 11 1988 10:05 | 64 |
| From: NACAD::MILRAT::UGRINOW "NICK UGRINOW 223-9605 MUSEUM MOUSE 05-Apr-1988 1644" 6-APR-1988 00:53
To: @[.DISTRIB]CLIENT,@[.DISTRIB]INTEREST
Subj: MAET Custom Course--Mgr's Intro to VALID
+---+---+
| M | A |
+---+---+
| E | T |
+---+---+
--------------------------------------------------------------------------------
M.A.E.T. Custom Courses Description
________________________________________________________________________________
Title MANAGERS INTRO TO VALID USING VAXSTATIONS
Instructor(s) Al Ramos/CTC-ETT, Digital
Date 12-MAY-88 - 12-MAY-88
Time 8 :15 - 5 :00
Location CAE TRAINING RM - MLO5-2/42C
Course Number 84MVA-01
Course Fee $ 350
Registration Log into COURSES software on MILRAT (223-0981).
Username and Password are both COURSES.
Cancellation YOU MUST WITHDRAW 5 WORK DAYS BEFORE CLASS START, OR
YOU WILL BE CHARGED THE FULL COURSE FEE!!!
Prerequisites
Manager - Level 10 and above
Audience
Managers needing to have a better understanding of VALID
Objective
Provide participants with introduction to functional capabilities
and available analysis programs used by VALID on the VAXstation.
Synopsis
This intensive one day program is intended to highlight the functional
capabilites and available analysis programs used by VALID on the VAXstation.
It is designed as an awareness vehicle to enhance the understanding you
may have about this CAE tool.
Topics include:
Overview
Hardware
OpDECLIB
DEC-STD-056
Minuteman Process
Summary of Unix Commands
Window Facility
Login - Exit
Functions for the Puck
Function Keys
Unix File Structure
GED Commands
Compiler Commands and Directives
Packager Commands and Directives
Timing Verifier Commands
Simulation
This class is a combination of lecture and lab excercises
--------------------------------------------------------------------------------
Maynard Area Engineering Training,
Design and Process Engineering, LES
|
| 9.21 | MAET STAFF LISTING | DELNI::ROUNDS | | Wed Apr 20 1988 14:45 | 62 |
|
____________________________________
| | | | | | | |
| d | i | g | i | t | a | l | INTEROFFICE MEMORANDUM
|____|____|____|____|____|____|____|
TO: Distribution DATE: 2 March 88
FROM: Gereda B. Pruitt
DEPT: M.A.E.T.
EXT: 223-6262
LOC: MLO1-3/U69
ENET: MILRAT::PRUITT
SUBJECT: Maynard Area Engineering Training Staff Changes
On February 29th, Laurie Dumont assumed responsibility for MAET's Custom
Courses program. In addition to this new role, Laurie will continue to
manage the Digital Video Network (DVN) program.
Mary Olian is joining MAET on a contract basis to handle the Technical
Seminar Series and the Satellite Network programs which were formerly
managed by Laurie. Mary has just completed an assignment with the HPS
training group in Marlboro and is familiar with the operations of satellite
programs.
I extend a special thank you to Sally Light for the excellent job she has
done as three month interium specialist for Custom Courses. For the
balance of FY88, Sally has accepted some very exciting and challenging new
responsibilities addressing some of the common needs across LES and SSM.
Please join me in thanking Laurie and Sally for their past program
successes and wishing them continued success, along with Mary, as they
transition into new roles.
MAET Contact Information:
-------------------------
Linda Watson-West LES/SCO/SSM Engineering 223-2905 MILRAT::WEST
Education Manager 225-5799 SHARE::WEST
Gereda Pruitt MAET Program Manager 223-6262 MILRAT::PRUITT
Sally Light University/Orientation 223-8194 MILRAT::LIGHT
Program Manager
Theresa McAllister MAET Group/University 223-6602 MILRAT::MCALLISTER
Programs/Orientation
Coodinator
Laurie Dumont Custom Courses/DVN 223-3674 MILRAT::DUMONT
Specialist
Nick Ugrinow Custom Courses/DVN 223-9605 MILRAT::UGRINOW
Coordinator
Mary Olian Technical Seminars/ 223-9612 MILRAT::OLIAN
Satellite Network
Specialist
Paula Coleman Technical Seminars/ 223-8628 MILRAT::COLEMAN
Satellite Network
Coordinator
|
| 9.22 | POSTSCRIPT COURSE | DELNI::ROUNDS | | Mon Apr 25 1988 15:16 | 45 |
| +---+---+
| M | A |
+---+---+
| E | T |
+---+---+
--------------------------------------------------------------------------------
M.A.E.T. Custom Courses Description
________________________________________________________________________________
Title POSTSCRIPT PAGE DESCRIPTION LANGUAGE
Instructor(s) Michael Fryd, MEFCO
Date 09-MAY-88 - 11-MAY-88
Time 8 :30 - 4 :30
Location CAE Training Room MLO5-2/42C
Course Number 84PSS-02
Course Fee $ 700
Registration Log into COURSES software on MILRAT (223-0981).
Username and Password are both COURSES.
Cancellation YOU MUST WITHDRAW 5 WORK DAYS BEFORE CLASS START, OR
YOU WILL BE CHARGED THE FULL COURSE FEE!!!
Prerequisites Some previous programming experience.
Audience Engineers and anyone needing to have an understanding of
PostScript.
Objectives Provide students with introduction to fundamentals of
PostScript text, graphics, and programming.
Synopsis This course has been developed especially for the use of
PostScript on Digital equipment. It begins with an
introduction to the power of PostScript, its features
and capabilities. Participants will learn how to describe
graphics and text in the PostScript language and hear an
overview of how typical applications communicate with
PostScript printers.
Participants will be able to produce simple PostScript
programs for text, graphics, and limited special effects.
--------------------------------------------------------------------------------
Maynard Area Engineering Training,
Design and Process Engineering, LES
+---+---+
|
| 9.23 | AUTODLY 2-Day Course | KEATS::CIASCHINI | | Thu Sep 08 1988 08:59 | 57 |
|
Instructor Linda Hart
Length 2 days
Registration For more information, contact the ECAD Documentation
& Training Group by sending mail to ECADSR::COURSES.
Prerequisite
Familiarity with DECSIM command language
Audience
Logic design engineers and technicians
Objective
To develop a working knowledge of AUTODLY, the timing verifier
by completing several labs and participating in classroom
discussions and lectures.
Synopsis
AUTODLY provides min-max timing verification of synchronous
gate-level designs. It is based on the DECSIM user interface
and network compiler and is restricted to DECSIM structural
models. This course is presented in two days. The first day
is intended to get you up and running quickly. Labs are basic
and straight forward. The second day, covers correlated and
simple skew, wiredelays, and, using a percentage of the delay
time. You will set up the complete AUTODLY environment for a
small design and determine the errors, and the solutions.
This course will cover:
o Understanding what timing checkers are and inserting
them into existing DECSIM library models.
o Preparing the working environment by writing setup files
and indirect files.
o Definition of AUTODLY States.
o Loading a network for AUTODLY.
o Activating a design with deposit files.
o Interpreting error reports.
o Examining the network to detect error locations.
o Understanding how skew is managed.
o Using wiredelays.
o Use a percentage of min-max timing.
|
| 9.24 | Creating An Effective Instructional Session | KEATS::CIASCHINI | | Thu Sep 08 1988 09:01 | 61 |
| Instructor Mary Elizabeth Raven, DIGITAL
Length 2 days long
Registration For more information, contact the ECAD Documentation
& Training Group by sending mail to ECADSR::COURSES.
Prerequisites
Students MUST come to the class prepared to work on a specific
instructional session. This instructional session must be one
that you have given, regularly give, or will be giving.
Objectives
--Understand lectures and demonstrations on the following:
o Preparing instructional objectives;
o Teaching the instructional objectives;
o Monitoring the class for feedback;
o Preparing a class for maximum retention;
o Maintaining student interest with voice, body movements,
AV equipment, and interpersonal interaction;
o Handling tangential questions, hecklers, and slow learners;
o Making and using slides, overhead transparencies, the
whiteboard, and other audio-visual aids.
--Prepare either a detailed lesson plan and discuss it with the
class for constructive criticism, or, if you want, practice
teaching part of that course.
--Plan labs for your course
--Critique slides, overheads, and other AV material. Improve
your use of AV materials.
Intended Audience
This two-day course is intended for all engineers, and managers
who create instructional sessions (teach).
Synopsis
The course will begin by discussing the difference between
teaching and presenting. This will be followed by a lecture on
instructional objectives and task analysis. You will work on
writing or improving the objectives and tasks in your course.
Next there will be a series of participative lectures on how
to teach to those objectives, how to prepare a session for
maximum retention, how to maintain student interest, and how
to use AV equipment effectively. Information from these
lectures will come from practicing engineering trainers, and
from research on education and cognitive sciences.
After the instructional session, you will have time to revise
your own instructional sessions by preparing a detailed lesson
plan or by preparing to teach part of the lesson. The class
will discuss and critique each lesson plan in a constructive
fashion.
|
| 9.25 | Developing DECLIB Symbols and Library Data | KEATS::CIASCHINI | | Thu Sep 08 1988 09:04 | 28 |
| Instructor Ted Kauppi
Length 3 days
Registration For more information, contact the ECAD Documentation
& Training Group by sending mail to ECADSR::COURSES.
Prerequisites o Introduction to VALID course or equivalent experience
o Working knowledge of VAX/VMS
o Working knowledge of EDT (or other editor)
Objectives At the end of this course students will be able to:
o Develop DECLIB equivalent bodies and library drawings
o Understand IEEE symbology
o Understand the library process as it relates to Valid's
software handling of body and library properties
Synopsis This course will prepare the attendee in the development
of DECLIB equivalent body symbols and library information
drawings. An understanding of body and library properties
found in DECLIB will be developed and utilized. Each
step of the library process is covered including the use
of Valid's Compiler and Packager.
The course is presented in a three day period consisting
of lecture, overview presentation, discussion, work-
station interaction, and lab assignments.
|
| 9.26 | Logic Simulation using Realmodel | KEATS::CIASCHINI | | Thu Sep 08 1988 09:08 | 29 |
| Instructor Abraham George, Digital
Length 2 days
Registration For more information, contact the ECAD Documentation
& Training Group by sending mail to ECADSR::COURSES.
Prerequisite DECSIM
Audience Designers, system simulation/application engineers and
managers (technical) who would like to expand their
system simulation capabilities using REALMODEL.
Objectives The goal of the course is to introduce REALMODEL and its
interface to DECSIM in creating hardware models for
system simulations.
Synopsis The REALMODEL course introduces the concept of using
the DECSIM REALMODEL interface to develop and use
hardware models in system simulation.
The course topics include:
o REALMODEL hardware
o DECSIM to REALMODEL hardware interface details
o Classifications of models
o Model development
o Translation to DECSIM files
o Simulation examples
|
| 9.27 | LES System Simulation Process for Users | KEATS::CIASCHINI | | Thu Sep 08 1988 09:09 | 40 |
| Instructor(s) Mary Beth Raven, et. al., DIGITAL
Length 3 days
Registration For more information, contact the ECAD Documentation
& Training Group by sending mail to ECADSR::COURSES.
Prerequisites
An understanding of logic design concepts.
Audience
Logic design engineers/technicians; CAD support personnel; anyone
who needs to understand a CAD simulation process.
Objectives
o To prepare a Valid schematic for simulation using ValidPACKAGER,
ValidCOMPILER, GSCALD, and S2DSIM.
o To obtain simulation models.
o To verify the logic and timing of a very simple design
using DECSIM, the logic simulator, and AUTODLY, the timing
verifier.
o To use or understand the purpose of the software utilities
and programs that are part of the simulation process.
Synopsis
This three-day course will take you from the process of
preparing a design for simulation to actually simulating
a design. It includes an introduction to Valid, the
schematic capture system; DECSIM, the logic simulator;
Hammer, a waveform display and analysis tool; Realmodel,
a hardware modeler; and AUTODLY, the timing verifier.
How simulation fits into the Low End System's Minuteman
Process is explained. We will give an overview of the
ESTG's (External Semicustom Technology Group) gate array
design process and Hudson's standard cell design process.
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| 9.28 | LES System Simulation Process for Managers | KEATS::CIASCHINI | | Thu Sep 08 1988 09:10 | 35 |
| Instructor(s) Mary Beth Raven et al, Digital
Length 1 day
Registration For more information, contact the ECAD Documentation
& Training Group by sending mail to ECADSR::COURSES.
Prerequisites o A basic working knowledge of VAX/VMS
o Familiarity with a VAXstation
o A working knowledge of EDT
o Familiarity with the hardware design process
Audience Managers of engineering design groups and CAD engineering
groups or anyone wishing an overview of the Simulation
process.
Objectives o To become familiar with the simulation tools and
libraries that engineers use to simulate.
o To understand the process of preparing a design for
simulation.
o To understand how simulation tools are used to verify
a design.
Synopsis This course compresses the three-day System Simulation
course into one day. Topics generally covered in-depth
in the three-day course are overviewed. Managers will
experience the process through a lab that has been set up
to be more automated than usual. Lectures will emphasize
the details and actual complexity of the process.
Managers will be exposed briefly to the Valid Schematic
Entry System; S2DSIM-- the translation program;
DECSIM--the logic simulator; AUTODLY--the timing
verifier. Obtaining simulation models and writing a
simulation plan will also be discussed.
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