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We've recently discovered a problem with the manufacturing test
equipment which is responsible for programming the IIC EEPROM on the
54-24829-DA (64MB Sdimm). Unfortunately some unknown quanity of
misprogrammed SDIMM's were shipped throughout the supply chain.
I suspect that you have some of the misprogrammed DIMM's.
If you know enough about the system to get to the SRM prompt,
It possible to dump the contents of the SEEPROM (requires at least one
good set of memory to load the SRM image into).
>>> e iic_mem3:0 -n 3F -b |more
replace the 3 in the above example with the dimm slot 0,1,2,3,4,5
:0 is the begining byte to start the dump (0 in this case)
3F is the number of bytes to dump (0-63)
Here's the latest version of data which should be programmed into the
SEEPROM during manufacturing. Miata only makes use of a subset of these
fields. (0 thru 22). We can make available a script which will
reprogram the SDIMM's in the field, but this script can cause much
havoc if improperly used.
/Dean
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
"5424829_REV6.XLS, 4/23/97" 8Mx72
Description 54-24829-xx comments
DEC HEX DA
0 (0) Total locations written to 80 one_twenty_eight
1 (1) Total bytes of EEprom (256) 8 two_fifty_six
2 (2) memory type (SDram) 4 sdram
3 (3) Number of ROW Addresses 0B eleven
4 (4) Number of Colums Adresses 0A ten
5 (5) Number of Banks on the DIMM 2 2 banks
6 (6) Module Data Width(1st Byte) 48 72 bits
7 (7) Module Data Width(2nd Byte) 0
8 (8) Module interface Levels 1 LVTTL
9 (9) SDram Cycle Time A0 10nS
10 (A) SDram Access Time 80 8.0nS
11 (B) Module's correction scheme 2 ECC
12 (C) Refresh Period 80 Normal/selfref
13 (D) Primary SDRAM width 4 4Mx4 SDRAM
14 (E) Error checking SDRAM width 4 4Mx4 SDRAM
15 (F) Min clk dly random coladdr 1 1clk
16 (10) SDram Burst Length Support 0E BL=8,4,2
17 (11) Sdram Device # of Banks 2 TWO
18 (12) Sdram Attribute:Cas Latency 6 THREE,TWO
19 (13) SDram Attribute:CS Latency 1 ZERO
20 (14) SDram Attribute:Wr Latency 1 ZERO
21 (15) Sdram Modules Attributes 1F buff/rege
22 (16) Sdram Device Attributes 6 PALL,PRE
23 (17) Min Clock Cycle CLx-1 F0 15nS
24 (18) MaxAccess/CLK CLx-1 90 9nS
25 (19) Min Clock Cycle CLx-2 0 not spec'd
26 (1A) MaxAccess/CLK CLx-2 0 not spec'd
27 (1B) Minimum Row Precharge tRP 1E 30nS
28 (1C) Min RowActv/RowActv tRRD 18 24nS
29 (1D) Min RAS/CAS delay tRCD 1E 30nS
30 (1E) MIN RAS pulse width tRAS 3C 60nS
31 (1F) Bank Density 8 32 Mbyte BANKS
32-61 (20-3D) Superset 0 (ZERO UNUSED)
62 (3E) SPD revision 1 rev 1
63 (3F) checksum 0-62 EC
64-- 125 Manufacturing data
64 (40) Manufacturer JEDEC ID 41 bee B
65 (41) 35 five 5
66 (42) 30 zero 0
67 (43) 30 zero 0
68 (44) 30 zero 0
69 (45) 30 zero 0
70 (46) 30 zero 0
71 (47) 30 zero 0
72 (48) Assembly Plant ID # 0 not specified
73 (49) ASCII(7bit) 35 five 5
74 (4A) ASCII(7bit) 34 four 4
75 (4B) ASCII(7bit) 32 two 2
76 (4C) ASCII(7bit) 34 four 4
77 (4D) ASCII(7bit) 38 eight 8
78 (4E) ASCII(7bit) 32 two 2
79 (4F) ASCII(7bit) 39 nine 9
80 (50) ASCII(7bit) 44 ABCD
81 (51) ASCII(7bit) 41 aye A
82-90 (52-5A) 0
91 (5B) Assembly Rev ASCII(7bit) 41 aye A
92 (5C) Assembly Rev ASCII(7bit) 31 one 1
93-127 (5D-7F) Not Used 0
128-255 Sys Integrator Data 0
|
| <<< WRKSYS::SYS_TOOLS:[NOTES$LIBRARY]XL_PERSONAL_WORKSTATION.NOTE;1 >>>
-< XL_PERSONAL_WORKSTATION >-
================================================================================
Note 380.3 64mb dimms on MIATA 3 of 3
WRKSYS::SOVIE "PKO3-2/T25" 223 lines 5-JUN-1997 10:48
-< exit >-
--------------------------------------------------------------------------------
I deleted 380.1 and have reposted it here (380.3)
There were 2 typo's in the 54-24829-DA chart.
decimal byte # 63 (checksum) changed from EC to ED.
decimal byte # 64 (manuf JEDEC ID) changed from 41 to 42 (ASCII 'B')
/Dean
<<< WRKSYS::SYS_TOOLS:[NOTES$LIBRARY]XL_PERSONAL_WORKSTATION.NOTE;1 >>>
-< XL_PERSONAL_WORKSTATION >-
================================================================================
Note 380.1 64mb dimms on MIATA 1 of 2
WRKSYS::SOVIE "PKO3-2/T25" 207 lines 4-JUN-1997 09:12
-< 64MB SDIMM problem >-
--------------------------------------------------------------------------------
I have re-entered the note from ALPHANOTES here with an additional
Deposit command shown and another table for the 16/32 Mbyte 54-25084 module
This is quite dangerous and could cause havoc if not used properly.
There are actually two known problems with the field supply of the
54-24829-DA (64Mbyte SDIMM).
The 1st problem is there were 205ea 54-24829-DA built up and shipped
into the supply chain with unqualified NEC SDRAM's. These NEC sdrams
fail to power-on init properly and causes MIATA to hang with a blank
screen. If you power off the machine and immediately repower up the
machine they NEC parts typically will power-up init properly and the
machine should work flawlessly until the next power-down-up event.
We've recovered most of the 205 NEC modules but some are still out
there.
The 2nd problem is as described below with the SEEPROM misprogrammed
Yesterday, there was a (unsubstanstiated) report of some 16 & 32 Mbyte
modules with possible SEEPROM mis-programming. We previously thought
this problem was with the 64Mbyte 54-24829-DA's only. I've notified
manufacturing test engineering of the latest developments.
/Dean
<<< VAXAXP::NOTES$:[NOTES$LIBRARY]ALPHANOTES.NOTE;1 >>>
-< Alpha Support Conference - Digital Internal Use Only >-
================================================================================
Note 104.2 PWS433a DIMM problems 2 of 3
WRKSYS::SOVIE "PKO3-2/T25" 94 lines 9-MAY-1997 15:15
--------------------------------------------------------------------------------
We've recently discovered a problem with the manufacturing test
equipment which is responsible for programming the IIC EEPROM on the
54-24829-DA (64MB Sdimm). Unfortunately some unknown quanity of
misprogrammed SDIMM's were shipped throughout the supply chain.
I suspect that you have some of the misprogrammed DIMM's.
If you know enough about the system to get to the SRM prompt,
It possible to dump the contents of the SEEPROM (requires at least one
good set of memory to load the SRM image into).
>>> e iic_mem3:0 -n 3F -b |more
replace the 3 in the above example with the dimm slot 0,1,2,3,4,5
:0 is the begining byte to start the dump (0 in this case)
3F is the number of bytes to dump (0-63)
Here's the latest version of data which should be programmed into the
SEEPROM during manufacturing. Miata only makes use of a subset of these
fields. (0 thru 22). We can make available a script which will
reprogram the SDIMM's in the field, but this script can cause much
havoc if improperly used.
You can selectively program individual bytes by using the following
command: program slot 1, byte 3, with the value 06
d iic_mem1:3 06 -b
1 is the slot to program (0-5)
3 is the byte to program in hex
06 is the data
/Dean
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Description 54-25084-xx 16M/32M UNBUFFERED SDIMM
"5425084_rev7.xls, 5/16/97" 2Mx72 4Mx72
DEC HEX BA DA
0 0 Total locations written to 80 80 one_twenty_eight
1 1 Total bytes of EEPROM 8 8 two_fifty_six
2 2 Memory Type 4 4 sdram
3 3 Number of ROW Addresses 0B 0B eleven
4 4 Number of Columns Addresses 9 9 nine 9
5 5 Number of Banks on the DIMM 1 2 1 / 2 banks
6 6 Module Data Width (1st Byte) 48 48 64 / 72 bits
7 7 Module Data Width (2nd Byte) 0 0
8 8 Module Interface Levels 1 1 LVTTL
9 9 SDram Cycle Time A0 A0 10 nS
10 A SDram Access Time 80 80 8.0 nS
11 B Module's correction scheme 2 2 NONE / ECC
12 C Refresh Period 80 80 Normal/selfref
13 D Primary SDRAM width 8 8 2Mx8 SDRAM
14 E Error checking SDRAM width 8 8 2Mx8 SDRAM
15 F Min clk dly random coladdr 1 1 1clk
16 10 SDram Burst Length Support 0E 0E "BL= 8,4,2"
17 11 Sdram Device # of Banks 2 2 TWO
18 12 Sdram Attribute: Cas Latency 6 6 "THREE,TWO"
19 13 SDram Attribute: CS Latency 1 1 ZERO
20 14 SDram Attribute: Wr Latency 1 1 ZERO
21 15 Sdram Modules Attributes 0 0 unbuffered
22 16 Sdram Device Attributes 6 6 "PALL,PRE"
23 17 Min Clock Cycle CLx-1 F0 F0 15nS
24 18 MaxAccess/CLK CLx-1 95 95 9.5nS
25 19 Min Clock Cycle CLx-2 0 0 not spec'd
26 1A MaxAccess/CLK CLx-2 0 0 not spec'd
27 1B Minimum Row Precharge tRP 1E 1E 30nS
28 1C Min RowActv/RowActv tRRD 18 18 24nS
29 1D Min RAS/CAS delay tRCD 1E 1E 30nS
30 1E MIN RAS pulse width tRAS 3C 3C 60nS
31 1F Bank Density 4 4 16 Mbyte BANKS
32-61 20-3D Superset (ZERO UNUSED) 0 0
62 3E SPD revision 1 1 rev 1
63 3F checksum 0-62 D5 D6
Manufacturing data
64 40 Manufacturer JEDEC ID 42 42 bee B
65 41 35 35 five 5
66 42 30 30 zero 0
67 43 30 30 zero 0
68 44 30 30 zero 0
69 45 30 30 zero 0
70 46 30 30 zero 0
71 47 30 30 zero 0
72 48 Assembly Plant ID # 0 0 not specified
73 49 ASCII(7bit) 35 35 five 5
74 4A ASCII(7bit) 34 34 four 4
75 4B ASCII(7bit) 32 32 two 2
76 4C ASCII(7bit) 35 35 five 5
77 4D ASCII(7bit) 30 30 zero 0
78 4E ASCII(7bit) 38 38 eight 8
79 4F ASCII(7bit) 34 34 four 4
80 50 ASCII(7bit) 42 44 B / D
81 51 ASCII(7bit) 41 41 aye A
82-90 52-5A 0 0
91 5B Assembly Rev ASCII(7bit) 44 44 dee D
92 5C Assembly Rev ASCII(7bit) 31 31 one 1
93-127 5D-7F Not Used 0 0
128-255 80-FF Sys Integrator Data 0 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
"5424829_REV6.XLS, 4/23/97" 8Mx72
Description 54-24829-xx comments
DEC HEX DA
0 (0) Total locations written to 80 one_twenty_eight
1 (1) Total bytes of EEprom (256) 8 two_fifty_six
2 (2) memory type (SDram) 4 sdram
3 (3) Number of ROW Addresses 0B eleven
4 (4) Number of Colums Adresses 0A ten
5 (5) Number of Banks on the DIMM 2 2 banks
6 (6) Module Data Width(1st Byte) 48 72 bits
7 (7) Module Data Width(2nd Byte) 0
8 (8) Module interface Levels 1 LVTTL
9 (9) SDram Cycle Time A0 10nS
10 (A) SDram Access Time 80 8.0nS
11 (B) Module's correction scheme 2 ECC
12 (C) Refresh Period 80 Normal/selfref
13 (D) Primary SDRAM width 4 4Mx4 SDRAM
14 (E) Error checking SDRAM width 4 4Mx4 SDRAM
15 (F) Min clk dly random coladdr 1 1clk
16 (10) SDram Burst Length Support 0E BL=8,4,2
17 (11) Sdram Device # of Banks 2 TWO
18 (12) Sdram Attribute:Cas Latency 6 THREE,TWO
19 (13) SDram Attribute:CS Latency 1 ZERO
20 (14) SDram Attribute:Wr Latency 1 ZERO
21 (15) Sdram Modules Attributes 1F buff/rege
22 (16) Sdram Device Attributes 6 PALL,PRE
23 (17) Min Clock Cycle CLx-1 F0 15nS
24 (18) MaxAccess/CLK CLx-1 90 9nS
25 (19) Min Clock Cycle CLx-2 0 not spec'd
26 (1A) MaxAccess/CLK CLx-2 0 not spec'd
27 (1B) Minimum Row Precharge tRP 1E 30nS
28 (1C) Min RowActv/RowActv tRRD 18 24nS
29 (1D) Min RAS/CAS delay tRCD 1E 30nS
30 (1E) MIN RAS pulse width tRAS 3C 60nS
31 (1F) Bank Density 8 32 Mbyte BANKS
32-61 (20-3D) Superset 0 (ZERO UNUSED)
62 (3E) SPD revision 1 rev 1
63 (3F) checksum 0-62 ED
64-- 125 Manufacturing data
64 (40) Manufacturer JEDEC ID 42 bee B
65 (41) 35 five 5
66 (42) 30 zero 0
67 (43) 30 zero 0
68 (44) 30 zero 0
69 (45) 30 zero 0
70 (46) 30 zero 0
71 (47) 30 zero 0
72 (48) Assembly Plant ID # 0 not specified
73 (49) ASCII(7bit) 35 five 5
74 (4A) ASCII(7bit) 34 four 4
75 (4B) ASCII(7bit) 32 two 2
76 (4C) ASCII(7bit) 34 four 4
77 (4D) ASCII(7bit) 38 eight 8
78 (4E) ASCII(7bit) 32 two 2
79 (4F) ASCII(7bit) 39 nine 9
80 (50) ASCII(7bit) 44 ABCD
81 (51) ASCII(7bit) 41 aye A
82-90 (52-5A) 0
91 (5B) Assembly Rev ASCII(7bit) 41 aye A
92 (5C) Assembly Rev ASCII(7bit) 31 one 1
93-127 (5D-7F) Not Used 0
128-255 Sys Integrator Data 0
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