| Title: | Alpha Support Conference |
| Notice: | This is a new Alphanotes, please read note 2.2 |
| Moderator: | VAXAXP::BERNARDO |
| Created: | Thu Jan 02 1997 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 128 |
| Total number of notes: | 617 |
Has someone a map how the cache bits are distributed between the
three cache modules in an a600. I have problems with bit 50 and
like to know witch simm this is. The tech manual didn't have this
in it.
Thanks
Ben
Palo Alto CA
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 42.1 | See WRKSYS::ALPHASTATION for some contact names... | XDELTA::HOFFMAN | Steve, OpenVMS Engineering | Fri Feb 07 1997 10:03 | 10 |
`a600'? As in AlphaStation 600 (Alcor?)... The AlphaStation conference is at WRKSYS::ALPHASTATION. Start with some of the folks that replied to 366, 603, 842, and 1398 over there... (I think you'll need to get someone with the service documentation involved, as there does not appear to be a readily documented way to determine which SIMM failed of the three SIMMs in the bcache.) | |||||
| 42.2 | alcor layout | JGO::POLFLIET | Mon Feb 10 1997 02:13 | 27 | |
Let me know if somethings is wrong (this is from the printsets).
We had several bad simms we placed in J15 while the ecc code
pointed to the simm in J13 (and vica versa).
J15: TAG_DATA<38:34>
DATA<63:32>
DATA<99:96>
DATA<115:112>
DATACHECK<7:4>
DATACHECK<15:12>
J14: TAG_DATA<33:26>
DATA<75:64>
DATA<91:80>
DATA<111:100>
DATA<127:116>
J13: TAG_DATA<25:20>
DATA<31:00>
DATA<79:76>
DATA<95:92>
DATACHECK<3:0>
DATACHECK<11:8>
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