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| Title: | VAX and Alpha VMS |
| Notice: | This is a new VMSnotes, please read note 2.1 |
| Moderator: | VAXAXP::BERNARDO |
|
| Created: | Wed Jan 22 1997 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 703 |
| Total number of notes: | 3722 |
350.0. "intstkpages , how to determine maximum value ?" by GIDDAY::SHCHIU () Wed Mar 19 1997 18:20
I have a customer has a 5 nodes vax cluster running vax/vms v6.1
three of the nodes are vax7730.
two of them has 1.5g memory, and the other one has 2g memory.
Due to oracle application problem, Oracle Vendor requests user to increase
intstkpages from 120 to 240 fof all vax7730 system.
^^^
after the changes, two of the nodes with 1.5g memory , only the primary
cpu get started after the reboot without error, and when user tried to
stop the 2nd and third cpu, it said the cpu was not start, when user
tried to start the cpu , it said cpu already started.
It ends up reboot and reset value back to 120 for intstkpages to fix
the problem .
The node with 2g memory , all three cpu were started fine.
looking at the source code SYSBOOT.LIS ,
the total pages for per cpu database :
( percpu database, boot stack, interupt stack, and 3 guard pages, rounded
up to a power of two, also include the for smp_cpu (
pages needed for any cpu's Per-CPU AREA -- vax7000 specific )
etc ... )
This clearly is resource problem .
Can someone explains to me , through the size of intstkpages, how the
system determine ( formula ) to decide which cpu can be started without
resource problem ? I seems to lost when look through the source code .
rgds
/stanley
X-62 + LOCATE_CPU_DATABASE - Locate per-CPU 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
2F1E 5463 .SBTTL + LOCATE_CPU_DATABASE - Locate per-CPU database
2F1E 5464
2F1E 5465 ;
2F1E 5466 ; Locate the PRIMARY CPU's per-CPU area on a page boundary that is naturally
2F1E 5467 ; aligned (to the size of the per-CPU area rounded up to the nearest power
2F1E 5468 ; of 2). To illustrate,
2F1E 5469 ;
2F1E 5470 ; PER-CPU AREA: (Total page count is a multiple of 2 and is so aligned)
2F1E 5471 ;
2F1E 5472 ; +---------------------------------------+
2F1E 5473 ; ! ! :BOO$GL_CPU_DATA
2F1E 5474 ; ! PRIMARY CPU'S PER-CPU DATABASE !
2F1E 5475 ; ! ! (CPU$C_PAGECNT Pages)
2F1E 5476 ; ! !
2F1E 5477 ; +---------------------------------------+
2F1E 5478 ; ! XXXXXXXXXX GUARD PAGE XXXXXXXXX ! (1 Page)
2F1E 5479 ; +---------------------------------------+
2F1E 5480 ; ! !
2F1E 5481 ; ! PRIMARY CPU'S BOOT STACK ! (1 Page)
2F1E 5482 ; ! !
2F1E 5483 ; +---------------------------------------+
2F1E 5484 ; ! XXXXXXXXXX GUARD PAGE XXXXXXXXX ! (1 Page)
2F1E 5485 ; +---------------------------------------+
2F1E 5486 ; ! ! :EXE$GL_INTSTK
2F1E 5487 ; ! PRIMARY CPU'S INTERRUPT !
2F1E 5488 ; ! STACK ! (SGN$GW_ISPPGCT Pages)
2F1E 5489 ; ! !
2F1E 5490 ; +---------------------------------------+
2F1E 5491 ; ! XXXXXXXXXX GUARD PAGE XXXXXXXXX ! (1 Page)
2F1E 5492 ; +---------------------------------------+
2F1E 5493 ; ! (POSSIBLE WASTED VA SPACE) !
2F1E 5494 ; (End of PER-CPU AREA)
2F1E 5495 ; +---------------------------------------+
2F1E 5496 ; ! ! :EXE$GL_SCB
2F1E 5497 ; ! SYSTEM CONTROL BLOCK (SCB) !
2F1E 5498 ; ! !
2F1E 5499 ; ! !
2F1E 5500 ; +---------------------------------------+
2F1E 5501 ; ! !
2F1E 5502 ; ! !
2F1E 5503 ;
2F1E 5504 ;
53 5733'CF 09 78 2F1E 5505 ASHL #VA$V_VPG,W^BOO$GL_CPUPGCT,R3 ; Convert page count to byte count
50 53 C2 2F24 5506 SUBL R3,R0 ; Lower currently allocated System VA
2F27 5507 ; space to make room for Primary's
2F27 5508 ; per-CPU area (Includes per-CPU
2F27 5509 ; database, Boot Stack, Interrupt
2F27 5510 ; Stack and 3 Guard pages, rounded
2F27 5511 ; up tp a power of 2 pages)
53 D7 2F27 5512 DECL R3 ; Calculate alignment bits
50 53 CA 2F29 5513 BICL R3,R0 ; Shave off low order bits to force
2F2C 5514 ; alignment of per-CPU area on desired
2F2C 5515 ; page boundary. Note that if any bits
2F2C 5516 ; are shaved off, then we've just
2F2C 5517 ; created wasted VA space between the
2F2C 5518 ; end of the per-CPU area and the base
2F2C 5519 ; of the SCB
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 141
X-62 + LOCATE_CPU_DATABASE - Locate per-CPU 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
572F'CF 50 52 C9 2F2C 5520 BISL3 R2,R0,W^BOO$GL_CPUDATA ; Set base of Primary's per-CPU area
50 0A00 C0 9E 2F32 5521 MOVAB CPU$C_STACK+512(R0),R0 ; Skip per-CPU database, Boot Stack
2F37 5522 ; guard page, Boot Stack page and
2F37 5523 ; first Interrupt Stack guard page.
53 0000'CF 3C 2F37 5524 MOVZWL W^SGN$GW_ISPPGCT,R3 ; Get age count form Interrupt Stack
53 53 09 78 2F3C 5525 ASHL #VA$V_VPG,R3,R3 ; Convert to bytes
50 53 C0 2F40 5526 ADDL R3,R0 ; Calculate base of Interrupt Stack
0000'CF 50 52 C9 2F43 5527 BISL3 R2,R0,W^EXE$GL_INTSTK ; Set base of Interrupt Stack
2F49 5528
53 0000'DF41 DE 2F49 5529 MOVAL @W^MMG$GL_SBR[R1],R3 ; Pointer to SPTE
50 58 59EC'CF C3 2F4F 5530 SUBL3 W^SCBPAGCT,R8,R0 ; Get # pages in PHD+SPT only
56 59EC'CF C0 2F55 5531 ADDL W^SCBPAGCT,R6 ; Get PFN of start of SYS PHD
56 B4000000 8F C9 2F5A 5532 10$: BISL3 #<PTE$C_ERKW!PTE$M_VALID!PTE$M_MODIFY!PTE$C_KOWN>, -
83 2F61 5533 R6,(R3)+ ; Map a page
56 D6 2F62 5534 INCL R6 ; Next PFN
F3 50 F5 2F64 5535 SOBGTR R0,10$ ; Map entire SYSPHD+SPT
50 5717'CF D0 2F67 5536 MOVL W^BOO$GL_GPTPGCT,R0 ; Count of Global page table pages
83 70000000 8F D0 2F6C 5537 20$: MOVL #PTE$C_URKW,(R3)+ ; Fill them as demand zero
F6 50 F5 2F73 5538 SOBGTR R0,20$ ;
2F76 5539 MAPSCB: ; Map SCB
16 09 EF 2F76 5540 EXTZV #VA$V_SVPN,#VA$S_SVPN,- ; Get SVPN
51 0000'CF 2F79 5541 W^EXE$GL_SCB,R1 ; of SCB
53 0000'DF41 DE 2F7D 5542 MOVAL @W^MMG$GL_SBR[R1],R3 ; Get addr of SPTE to fill
51 59EC'CF D0 2F83 5543 MOVL W^SCBPAGCT,R1 ; Get # pages of SCB
50 59F4'CF F7 8F 78 2F88 5544 ASHL #-VA$V_VPG,W^SCBPHADDR,R0 ; Get PFN of start of SCB
B4000000 8F C9 2F8F 5545 10$: BISL3 #<PTE$C_ERKW!PTE$M_VALID!PTE$M_MODIFY!PTE$C_KOWN>,-
83 50 2F95 5546 R0,(R3)+ ; Map next SPTE
50 D6 2F97 5547 INCL R0 ; Step to next PFN
F3 51 F5 2F99 5548 SOBGTR R1,10$ ; Map whole SCB
2F9C 5549 MAPISTK: ; Map Interrupt Stack
16 09 EF 2F9C 5550 EXTZV #VA$V_SVPN,#VA$S_SVPN,- ; Get SVPN for Int Stack
51 0000'CF 2F9F 5551 W^EXE$GL_INTSTK,R1
53 0000'DF41 DE 2FA3 5552 MOVAL @W^MMG$GL_SBR[R1],R3 ; SVASPT + 4
51 0000'CF 3C 2FA9 5553 MOVZWL W^SGN$GW_ISPPGCT,R1 ; Get page count for Int Stack
0E18 30 2FAE 5554 10$: BSBW ALLOCPFN ; Allocate a page
50 B4000000 8F C9 2FB1 5555 BISL3 #<PTE$C_ERKW!PTE$M_VALID!PTE$M_MODIFY!PTE$C_KOWN>, -
73 2FB8 5556 R0,-(R3) ; Fill Valid map entry
F2 51 F5 2FB9 5557 SOBGTR R1,10$ ; Map entire Interrupt Stack
2FBC 5558
2FBC 5559 ;
2FBC 5560 ; Map the per-CPU database and boot stack in front of the interrupt stack
2FBC 5561 ; guard page.
2FBC 5562 ;
2FBC 5563 MAPCPU:
16 09 EF 2FBC 5564 EXTZV #VA$V_SVPN,#VA$S_SVPN,- ; Get SVPN of
51 572F'CF 2FBF 5565 W^BOO$GL_CPUDATA,R1 ; per-CPU database
53 0000'DF41 DE 2FC3 5566 MOVAL @W^MMG$GL_SBR[R1],R3 ; Get addr of SPTE to fill
2FC9 5567
2FC9 5568 ;
2FC9 5569 ; If the per-CPU database is greater than a page, no attempt is made
2FC9 5570 ; in the following code to make the pages physically contiguous. This
2FC9 5571 ; requires that all per-CPU database cells required for power fail
2FC9 5572 ; restart, starting/stopping a CPU, and some types of error handling must
2FC9 5573 ; be on the first page if they are referenced using physical addresses.
2FC9 5574 ;
2FC9 5575
51 02 D0 2FC9 5576 MOVL #CPU$C_PAGECNT,R1 ; Get # pages of per-CPU area
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 142
X-62 + LOCATE_CPU_DATABASE - Locate per-CPU 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
0DFA 30 2FCC 5577 10$: BSBW ALLOCPFN ; Allocate a page
F0000000 8F C9 2FCF 5578 BISL3 #<PTE$C_URKW!PTE$M_VALID!PTE$C_KOWN>,-
83 50 2FD5 5579 R0,(R3)+ ; Map next SPTE
F2 51 F5 2FD7 5580 SOBGTR R1,10$ ; Map entire per-CPU database
53 04 C0 2FDA 5581 ADDL2 #4,R3 ; Skip Boot Stack guard page SPTE
0DE9 30 2FDD 5582 BSBW ALLOCPFN ; Allocate a page
B4000000 8F C9 2FE0 5583 BISL3 #<PTE$C_ERKW!PTE$M_VALID!PTE$M_MODIFY!PTE$C_KOWN>,-
63 50 2FE6 5584 R0,(R3) ; Map Boot Stack page
2FE8 5585 WHAMI R2 ; Get this CPU's ID
16 09 EF 3104 5586 EXTZV #VA$V_SVPN,#VA$S_SVPN,- ; Get SVPN of base of P0 page table
50 5A2C'CF 3107 5587 W^BOO_P0PT_MAP,R0 ; pages
50 52 C0 310B 5588 ADDL2 R2,R0 ; Index to this CPU's P0 page table page
63 02000000 8F C9 310E 5589 BISL3 #PTE$M_WINDOW,(R3),- ; Double map this CPU's Boot Stack in high
0000'DF40 3115 5590 @W^MMG$GL_SBR[R0] ; SVA to be used as a P0 page table page
53 0C C2 3119 5591 SUBL #<CPU$C_PAGECNT*4>+4,R3 ; Point to 1st SPTE of per-CPU database
51 572F'CF D0 311C 5592 MOVL W^BOO$GL_CPUDATA,R1 ; Get address of base
3121 5593
3121 5594
----------------------------------------------
X-62 + SMP_SPT - Calculate pages needed for 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
274E 4816 .SBTTL + SMP_SPT - Calculate pages needed for any CPU's Per-CPU Area
274E 4817
274E 4818 ;
274E 4819 ; Calculate pages needed for any CPU'a per-CPU area.
274E 4820 ;
274E 4821 ; The page count of the per-CPU area must be rounded up to a power of 2.
274E 4822 ; This resulting page count defines the scope of the FIND_CPU_DATA Macro
274E 4823 ; and includes the per-CPU database, a guard page, the per-CPU boot stack,
274E 4824 ; another guard page, the interrupt stack and another guard page.
274E 4825 ;
274E 4826 ; By locating the pre-CPU database on a natural page boundary (aligned to
274E 4827 ; the calculated power of 2), one can simply shave off a bunch of bits from
274E 4828 ; any virtual address within the per-CPU area - for example the Interrupt
274E 4829 ; Stack Pointer - in order to locate the base of the per-CPU database itself,
274E 4830 ; which is guaranteed to be at the base of the overall per-CPU data area.
274E 4831 ;
274E 4832 SMP_SPT:
50 0000'CF 3C 274E 4833 MOVZWL W^SGN$GW_ISPPGCT,R0 ; Pages of interrupt stack +
50 06 C0 2753 4834 ADDL #CPU$C_PAGECNT+2+2,R0 ; # of pages for per-CPU database +
2756 4835 ; boot stack page and guard page +
2756 4836 ; 2 interrupt stack guard pages
51 03 D0 2756 4837 MOVL #3,R1 ; Init power of 2 (Assumes 8 pages min)
52 01 51 78 2759 4838 100$: ASHL R1,#1,R2 ; Get next power of 2
50 52 D1 275D 4839 CMPL R2,R0 ; Is rounded value large enough yet?
05 18 2760 4840 BGEQ 110$ ; BR if Yes
F3 51 19 F2 2762 4841 AOBLSS #25,R1,100$ ; Else go up to next power of 2
00 2766 4842 HALT ; Should never get here
2767 4843
5733'CF 52 D0 2767 4844 110$: MOVL R2,W^BOO$GL_CPUPGCT ; Rounded page count of per-CPU area
276C 4845 ; (Includes per-CPU database, boot
276C 4846 ; stack, 3 guard pages and interrupt
276C 4847 ; stack)
276C 4848 ;
276C 4849 ; Now that the per-CPU area page count has been determined, reserve a set
276C 4850 ; of per-CPU area SPTEs for each CPU that might exist for this processor
276C 4851 ; configuration.
276C 4852 ;
276C 4853 ; In the case of a Multiprocessor configuration, an extra CPU's worth of
276C 4854 ; per-CPU area SPTEs is reserved for the following reason. It is important
276C 4855 ; that the per-CPU area be aligned on a page boundary consistent with the
276C 4856 ; power of 2 factor calculated above. The SPTE allocation mechanisms will be
276C 4857 ; asked (for each additional CPU) for twice the number of SPTEs needed for a
276C 4858 ; complet per-CPU area, then the per-CPU area is properly aligned within the
276C 4859 ; returned virtual address range, and then any virtual address slop left over
276C 4860 ; either below or above the aligned per-CPU area will be returned to the pool
276C 4861 ; of free SPTEs. So for the period of time where the per-CPU area's SPTEs
276C 4862 ; are being allocated, more SPTEs (double) are temporarily needed until the
276C 4863 ; per-CPU area is properly aligned, at which point the extra SPTEs will be
276C 4864 ; returned.
276C 4865 ;
276C 4866 .list meb
276C 4867 CPUDISP <<780,NO_MP>,- ; If the system is potentially a
276C 4868 <750,NO_MP>,- ; Multiprocessor, reserve a bunch
276C 4869 <730,NO_MP>,- ; more SPTEs for use by the other
276C 4870 <790,NO_MP>,- ; CPUs' per-CPU areas in the future.
276C 4871 <UV1,NO_MP>,- ;
276C 4872 <UV,NO_MP>,- ;
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 123
X-62 + SMP_SPT - Calculate pages needed for 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
276C 4873 <420,NO_MP>,- ;
276C 4874 <43, 130$>,- ;
276C 4875 <440,130$>,- ;
276C 4876 <46, 130$>,- ;
276C 4877 <4A, 130$>,- ;
276C 4878 <49, 130$>,- ;
276C 4879 <60, 130$>,- ;
276C 4880 <UV2,NO_MP>,- ;
276C 4881 <520,111$>,- ;
276C 4882 <550,111$>,- ;
276C 4883 <600,113$>,- ;
276C 4884 <650,112$>,- ;
276C 4885 <670,113$>,- ;
276C 4886 <660,113$>,- ;
276C 4887 <690,113$>,- ;
276C 4888 <700,113$>,- ;
276C 4889 <8SS,115$>,- ;
276C 4890 <8NN,120$>,- ;
276C 4891 <8PS,125$>,- ;
276C 4892 <9AQ,140$>,- ;
276C 4893 <9CC,130$>,- ;
276C 4894 <9RR,130$>,- ;
276C 4895 <1202,130$>,- ;
276C 4896 <1302,130$>,- ;
276C 4897 <1303,113$>,- ;
276C 4898 <1701,150$>,- ;
276C 4899 >,- ;
276C 4900 ENVIRON=VMB,CONTINUE=YES
16 01 00000000'GF 8F 276C CASEB G^EXE$GB_CPUTYPE,#$$BASE,#$$LIMIT
2774 30543$:
0146' 2774 .IIF EQ $$GENSW, .SIGNED_WORD NO_MP-30543$
0146' 2776 .IIF EQ $$GENSW, .SIGNED_WORD NO_MP-30543$
0146' 2778 .IIF EQ $$GENSW, .SIGNED_WORD NO_MP-30543$
0146' 277A .IIF EQ $$GENSW, .SIGNED_WORD NO_MP-30543$
00E0' 277C .IIF EQ $$GENSW, .SIGNED_WORD 115$-30543$
00E5' 277E .IIF EQ $$GENSW, .SIGNED_WORD 120$-30543$
0146' 2780 .IIF EQ $$GENSW, .SIGNED_WORD NO_MP-30543$
0031' 2782 .IIF EQ $$GENSW, .SIGNED_WORD 30471$-30543$
002E 2784 .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
0043' 2786 .IIF EQ $$GENSW, .SIGNED_WORD 30472$-30543$
005C' 2788 .IIF EQ $$GENSW, .SIGNED_WORD 30473$-30543$
002E 278A .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
002E 278C .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
0101' 278E .IIF EQ $$GENSW, .SIGNED_WORD 140$-30543$
002E 2790 .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
002E 2792 .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
00F0' 2794 .IIF EQ $$GENSW, .SIGNED_WORD 125$-30543$
006F' 2796 .IIF EQ $$GENSW, .SIGNED_WORD 30474$-30543$
0080' 2798 .IIF EQ $$GENSW, .SIGNED_WORD 30475$-30543$
0097' 279A .IIF EQ $$GENSW, .SIGNED_WORD 30476$-30543$
002E 279C .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
002E 279E .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
00B0' 27A0 .IIF EQ $$GENSW, .SIGNED_WORD 30477$-30543$
0089 31 27A2 BRW 30478$
27A5 30471$:
01 00 0000000F'GF 8F 27A5 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
27AD 30544$:
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 124
X-62 + SMP_SPT - Calculate pages needed for 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
010D' 27AD .SIGNED_WORD NO_MP-30544$
010D' 27AF .SIGNED_WORD NO_MP-30544$
0106 31 27B1 BRW NO_MP
0077 31 27B4 BRW 30478$
27B7 30472$:
06 01 0000000F'GF 8F 27B7 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
27BF 30545$:
007C' 27BF .SIGNED_WORD 112$-30545$
00AA' 27C1 .SIGNED_WORD 130$-30545$
00AA' 27C3 .SIGNED_WORD 130$-30545$
00FB' 27C5 .SIGNED_WORD NO_MP-30545$
000E 27C7 .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
000E 27C9 .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
0072' 27CB .SIGNED_WORD 111$-30545$
005E 31 27CD BRW 30478$
27D0 30473$:
03 01 0000000F'GF 8F 27D0 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
27D8 30546$:
0073' 27D8 .SIGNED_WORD 113$-30546$
0091' 27DA .SIGNED_WORD 130$-30546$
0008 27DC .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
0091' 27DE .SIGNED_WORD 130$-30546$
004B 31 27E0 BRW 30478$
27E3 30474$:
02 02 0000000F'GF 8F 27E3 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
27EB 30547$:
007E' 27EB .SIGNED_WORD 130$-30547$
0006 27ED .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
007E' 27EF .SIGNED_WORD 130$-30547$
003A 31 27F1 BRW 30478$
27F4 30475$:
05 01 0000000F'GF 8F 27F4 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
27FC 30548$:
004F' 27FC .SIGNED_WORD 113$-30548$
006D' 27FE .SIGNED_WORD 130$-30548$
004F' 2800 .SIGNED_WORD 113$-30548$
006D' 2802 .SIGNED_WORD 130$-30548$
004F' 2804 .SIGNED_WORD 113$-30548$
004F' 2806 .SIGNED_WORD 113$-30548$
0023 31 2808 BRW 30478$
280B 30476$:
06 01 0000000F'GF 8F 280B CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
2813 30549$:
0038' 2813 .SIGNED_WORD 113$-30549$
000E 2815 .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
000E 2817 .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
0056' 2819 .SIGNED_WORD 130$-30549$
0056' 281B .SIGNED_WORD 130$-30549$
000E 281D .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
001E' 281F .SIGNED_WORD 111$-30549$
000A 31 2821 BRW 30478$
2824 30477$:
00 01 0000000F'GF 8F 2824 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
282C 30550$:
004E' 282C .SIGNED_WORD 150$-30550$
282E 30478$:
282E 4901 .nlist meb
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 125
X-62 + SMP_SPT - Calculate pages needed for 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
0089 31 282E 4902 BRW NO_MP ; On unknown type, assume Uniprocessor
2831 4903
54 000014C8 8F C0 2831 4904 111$: ADDL #<<10*512>+200>,R4 ; Account for CIO mappings and other
2838 4905 ; unique Cirrus mappings.
007F 31 2838 4906 BRW NO_MP
283B 4907
000D'CF 02 91 283B 4908 112$: CMPB #2,W^EXE$GB_CPUDATA+12+1 ; Is this really a Mayfair II?
78 12 2840 4909 BNEQ NO_MP ; Br if not, continue with no SMP
54 0000020C 8F C0 2842 4910 ADDL #<256+1+9>+<256+2>,R4 ; Account for SII and LANCE mappings
6F 11 2849 4911 BRB NO_MP ; No SMP
284B 4912
54 00000120 8F C0 284B 4913 113$: ADDL #288,R4 ; Get more SPTEs for the SGEC
66 11 2852 4914 BRB NO_MP ; No SMP
2854 4915
52 10 C4 2854 4916 115$: MULL #CPU$C_8SS_CPUS,R2 ; Reserve enough for all potential CPUs
5C 11 2857 4917 BRB PLUS_ONE ; Join common code
2859 4918
03 E0 2859 4919 120$: BBS #PR8NN$V_RXDB_UNI,-
5B 5A14'CF 285B 4920 W^CPUDATA+8,NO_MP ; Branch if this is a Uniprocessor
52 02 C4 285F 4921 MULL #CPU$C_8NN_CPUS,R2 ; This is a Multiprocessor configuration
51 11 2862 4922 BRB PLUS_ONE ; Join common code
2864 4923
52 04 C4 2864 4924 125$: MULL #CPU$C_8PS_CPUS,R2 ; Reserve enough for all potential CPUs
4C 11 2867 4925 BRB PLUS_ONE ; Join common code
2869 4926
52 5A20'CF C4 2869 4927 130$: MULL W^BOO_CPUS,R2 ; Reserve enough for all CPUs present
52 5A30'CF C0 286E 4928 ADDL2 W^BOO_EXTRA_SPTS,R2 ; Add additional SPTs
40 11 2873 4929 BRB PLUS_ONE ; Join common code
2875 4930
52 04 C4 2875 4931 140$: MULL2 #CPU$C_9AQ_CPUS,R2 ; Reserve enough for all potential CPUs
3B 11 2878 4932 BRB PLUS_ONE ; Join common code
287A 4933
52 5A20'CF C4 287A 4934 150$: MULL W^BOO_CPUS,R2 ; Reserve enough for all CPUs present
52 5A30'CF C0 287F 4935 ADDL2 W^BOO_EXTRA_SPTS,R2 ; Add additional SPTs
2884 4936 ;
2884 4937 ; This next section will get a count of the pages needed for console for the
2884 4938 ; 1701 cpu. This includes the HWRPB and all of the entries in the CRB.
2884 4939
53 000000B0 8F DB 2884 4940 MFPR #PR1701$_CHALT,R3 ; Address of console structure
50 0C A3 000001FF 8F C1 288B 4941 ADDL3 #511, - ; Get # of bytes in HWRPB rounded to
2894 4942 CHALT$L_HWRPB_SIZE(R3), R0 ; nearest page
2894 4943
00005A34'EF 50 F7 8F 78 2894 4944 ASHL #-VA$V_VPG, R0, - ; convert to # of pages
289D 4945 CONSOLE_PAGE_1701
53 10 A3 D0 289D 4946 MOVL CHALT$L_HWRPB_PHYS_ADR(R3), R3
28A1 4947 ; Get HWRPB base address
53 00C0 C3 C0 28A1 4948 ADDL HWRPB$Q_CRB_OFFSET(R3), R3
28A6 4949 ; Get CRB base address
28 A3 C0 28A6 4950 ADDL HWRPB_CRB$Q_PAGE_COUNT(R3),-
00005A34'EF 28A9 4951 CONSOLE_PAGE_1701
52 00005A34'EF C0 28AE 4952 ADDL CONSOLE_PAGE_1701, R2 ; Add in Console callback routines
28B5 4953 ; and HWRPB
28B5 4954 ;;; BRB PLUS_ONE ; Join common code
28B5 4955
28B5 4956 PLUS_ONE:
52 5733'CF C0 28B5 4957 ADDL2 W^BOO$GL_CPUPGCT,R2 ; Add one more CPU's worth of SPTEs
28BA 4958 ; to ensure successful allocation and
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 126
X-62 + SMP_SPT - Calculate pages needed for 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
28BA 4959 ; alignment of per-CPU area later.
28BA 4960 NO_MP:
54 52 C0 28BA 4961 ADDL R2,R4 ; Add to SPT requirement
28BD 4962 ;
28BD 4963 ; Also reserved is an extra SPTE for each potential CPU to double-map
28BD 4964 ; the per-CPU boot stack, which serves as a P0 page table page when enabling
28BD 4965 ; memory management. The VA that is used to access this page when enabling
28BD 4966 ; memory management must be a high S0 space VA to accomodate large PFNs (in
28BD 4967 ; other words, to ensure that the temporary P0 page table can entirely lie
28BD 4968 ; within S0 space).
28BD 4969 ;
54 20 C0 28BD 4970 ADDL2 #CPU$C_MAX_CPUS,R4 ; Reserve an SPTE for each potential CPU
28C0 4971
28C0 4972 ;
28C0 4973 ; Count pages needed for global pages
28C0 4974 ;
51 0000'CF 02 78 28C0 4975 GPCNT: ASHL #2,W^SGN$GL_MAXGPGCT,R1 ; Requested number of global pages
28C6 4976
51 01FF C1 9E 28C6 4977 MOVAB 511(R1),R1 ; Round to page boundary
51 51 F7 8F 78 28CB 4978 ASHL #-VA$V_VPG,R1,R1 ; Convert to page count
5717'CF 51 D0 28D0 4979 MOVL R1,W^BOO$GL_GPTPGCT ; Save count of Global page table
54 51 C0 28D5 4980 ADDL R1,R4 ; Add to SPT total
28D8 4981 ;
28D8 4982 ; Note - SCB page count is calculated by CPU-specific code in the CPU_nnn
28D8 4983 ; paragraphs.
28D8 4984 ;
54 59EC'CF C0 28D8 4985 ADDL W^SCBPAGCT,R4 ; Add SCB pages to SPT total
59F0'CF 59EC'CF 09 78 28DD 4986 ASHL #VA$V_VPG,W^SCBPAGCT,W^SCBBYTCT ; Save SCB size in bytes
28E5 4987
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 127
X-62 + CACHE_SPT - Establish the SPT requir 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
28E5 4989 .SBTTL + CACHE_SPT - Establish the SPT required for the VBN cache
28E5 4990
28E5 4991 ;
28E5 4992 ; Calculate the maximum size of the VBN cache and allocate SPTEs
28E5 4993 ; to map it. The size is physical memory minus system nonpaged
28E5 4994 ; "stuff" minus room for one process. Note this is the maximum
28E5 4995 ; size of the cache. It will probably be smaller. The "stuff" is
28E5 4996 ; SGN$GL_NPAGEDYN
28E5 4997 ; SGN$GL_FREELIM
28E5 4998 ; MPW$GW_LOLIM
28E5 4999 ; SGN$GL_SYSDWSCT
28E5 5000 ; system code+data
28E5 5001 ; plus room for one process - SGN$GL_MAXWSCNT
28E5 5002 ;
28E5 5003 CACHE_SPT:
00005A47'EF 54 D1 28E5 5004 CMPL R4,USABLE_SPT_LEN ; See if any SPTEs left
0F 14 28EC 5005 BGTR 0$ ; If not, don't adjust so we'll get
28EE 5006 ; a VASOVF message at VERIFY_SPT
5A67'CF C3 28EE 5007 SUBL3 W^MEM_LO_PFN,- ; Calculate amount of memory we have
52 5A6B'CF 28F2 5008 W^MEM_HI_PFN,R2
28F6 5009 ASSUME CACHE$V_ALLOW EQ 8
07 00000001'EF E8 28F6 5010 BLBS CACHE$GL_FLAGS+1,1$ ; If LBS allocate cache SPTEs
0000'CF D4 28FD 5011 0$: CLRL W^CACHE$GL_PTES ; No cache PTEs
007F 31 2901 5012 BRW 30$ ; Quit now
2904 5013
F7 8F 78 2904 5014 1$: ASHL #-VA$S_BYTE,- ; Convert byte cnt to page cnt
50 0000'CF 2907 5015 W^SGN$GL_NPAGEDYN,R0 ; Byte cnt already even number of pages
52 50 C2 290B 5016 SUBL R0,R2 ; Nonpaged pool memory never available
52 0000'CF C2 290E 5017 SUBL W^SGN$GL_FREELIM,R2 ; Base part of free list not available
50 0000'CF 3C 2913 5018 MOVZWL W^MPW$GW_LOLIM,R0 ; Need LOLIM as a longword
52 50 C2 2918 5019 SUBL R0,R2 ; Base part of modified list not available
52 0000'CF C2 291B 5020 SUBL W^SGN$GL_SYSDWSCT,R2 ; System working set memory not for available
52 0000'CF C2 2920 5021 SUBL W^SGN$GL_MAXWSCNT,R2 ; Room for one process
52 00000400 8F C2 2925 5022 SUBL #EXEC_SPTES,R2 ; Exec code/data memory not available
50 52 0000007F 8F C1 292C 5023 ADDL3 #127,R2,R0 ; Divide (round up) by 128
50 50 F9 8F 78 2934 5024 ASHL #-<VA$V_VPG-2>,R0,R0 ; Number of pages of PTEs to map cache
52 50 C2 2939 5025 SUBL R0,R2 ; Number of pages available to cache
02 18 293C 5026 BGEQ 5$ ; Do we have less memory than are
293E 5027 ; parameters allow for
52 D4 293E 5028 CLRL R2 ; Set CACHE Size to Zero
2940 5029 5$:
0000'CF 52 D1 2940 5030 CMPL R2,W^SGN$GL_CACHEPTES ; Minimize with SYSGEN value
05 15 2945 5031 BLEQ 10$ ; If LEQ R2 is already correct
52 0000'CF D0 2947 5032 MOVL W^SGN$GL_CACHEPTES,R2 ; SYSGEN value is lower
0000'CF 52 D0 294C 5033 10$: MOVL R2,W^CACHE$GL_PTES ; Save max number of pages for cache
54 52 C0 2951 5034 ADDL R2,R4 ; One SPTE for each cache page
50 52 0000007F 8F C1 2954 5035 ADDL3 #127,R2,R0 ; Divide (round up) by 128
50 50 F9 8F 78 295C 5036 ASHL #-<VA$V_VPG-2>,R0,R0 ; Number of pages of PTEs to map cache
54 50 C0 2961 5037 ADDL R0,R4 ; One SPTE for each page of SPTE
51 00005A47'EF D0 2964 5038 20$: MOVL USABLE_SPT_LEN,R1 ; Get maximum usable SPTEs
51 54 D1 296B 5039 CMPL R4,R1 ; Is system space too big?
13 15 296E 5040 BLEQ 30$ ; If LEQ No
50 54 51 C3 2970 5041 SUBL3 R1, R4, R0 ; R0 = OVERAGE
0000'CF 50 C2 2974 5042 SUBL2 R0, W^CACHE$GL_PTES ; Adjust Cache Size
05 18 2979 5043 BGEQ 25$ ; CACHE SIZE GO NEGATIVE
0000'CF 00 9A 297B 5044 MOVZBL #0, W^CACHE$GL_PTES ; Set Size to Zero
2980 5045 25$:
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 128
X-62 + CACHE_SPT - Establish the SPT requir 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
54 51 D0 2980 5046 MOVL R1, R4 ; Set SPT Size to MAX USABLE
2983 5047 30$:
2983 5048
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 129
X-62 + VERIFY_SPT - Verify S0 address space 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
2983 5050 .SBTTL + VERIFY_SPT - Verify S0 address space is enough for P0 page table
2983 5051
2983 5052 ;
2983 5053 ; Verify that system virtual address space is large enough to hold the maximum
2983 5054 ; temporary P0 page table used to map physical memory during the transition of
2983 5055 ; memory management from disabled state to enabled state. The longest P0 page
2983 5056 ; table is driven by the maximum PFN number that may require mapping, which will
2983 5057 ; be the actual highest page in memory or the last page in 512MB of memory, whichever
2983 5058 ; is lower.
2983 5059 ;
2983 5060 VERIFY_SPT:
2983 5061
51 5A6B'CF D0 2983 5062 MOVL W^MEM_HI_PFN,R1 ; Get highest Page Frame Number
51 00100000 8F D1 2988 5063 CMPL #^X100000,R1 ; Is it greater than 512MB/2**9?
07 1E 298F 5064 BGEQU 15$ ; If GEQU No, Use lower value
51 00100000 8F D0 2991 5065 MOVL #^X100000,R1 ; Use lower value = 512MB/2**9
51 54 D1 2998 5066 15$: CMPL R4,R1 ; System space big enough to hold
299B 5067 ; longest P0 page table?
03 1E 299B 5068 BGEQU 20$ ; If GEQU Yes
54 51 D0 299D 5069 MOVL R1,R4 ; Extend system space to accomodate
29A0 5070 ; longest P0 page table (which in turn
29A0 5071 ; allows us to map the highest accessible
29A0 5072 ; PFN on transition of MAPEN from 0 to 1)
29A0 5073 ;
29A0 5074 ; Trim off the system page table to determine the final SPT page count.
29A0 5075 ;
54 7F A4 9E 29A0 5076 20$: MOVAB 127(R4),R4 ; Round to page boundary
51 54 F9 8F 78 29A4 5077 ASHL #-<VA$V_VPG-2>,R4,R1 ; Convert to pages
54 51 C0 29A9 5078 ADDL R1,R4 ; Add pages of SPT to map
29AC 5079
29AC 5080 ; Verify that the size of system address space has not exceeded the
29AC 5081 ; architectural bounds of S0 space, or system space if the processor
29AC 5082 ; implements the S0 extension feature.
29AC 5083
00200000 8F 54 D1 29AC 5084 CMPL R4,#^X200000 ; Is system space too big for S0 region?
03 1A 29B3 5085 BGTRU 30$ ; If GTRU yes
016D 31 29B5 5086 BRW 100$ ; No, continue
29B8 5087
29B8 5088 ; Some processors have implemented an extension of S0 space into what
29B8 5089 ; we'll call system space (i.e., S0 and S1 spaces have been concatenated
29B8 5090 ; into one 2 Gb region). If system space has exceeded 1 Gb in length,
29B8 5091 ; check if we're executing on one of those systems and use of extended
29B8 5092 ; physical memory has not been dis-allowed. Note that the last page of
29B8 5093 ; system space is reserved for use in passing GPR specifiers during VAX
29B8 5094 ; instruction emulation, so system space is REALLY 2 Gb minus 1 page.
29B8 5095
29B8 5096 30$: CPUDISP <<9AQ,40$>,- ; All CPUs which support S0 extension
29B8 5097 <1302,50$>,- ; should be present in this CPUDISP
29B8 5098 <1701,50$>>,-
29B8 5099 ENVIRON=VMB,CONTINUE=YES
00E8 31 29FD 5100 BRW 90$ ; If no support, die now
2A00 5101
2A00 5102 ; Enter here at 40$ for machines which were field-upgradable to support
2A00 5103 ; the S0 extension (only the VAX 9000). All others should enter at 50$.
2A00 5104
5A41'CF 89 2A00 5105 40$: BISB3 W^XVA_CPU_REV,- ; Check for CPU rev
50 5A3D'CF 2A04 5106 W^XPA_CPU_REV,R0 ; (Check both XVA & XPA here)
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 130
X-62 + VERIFY_SPT - Verify S0 address space 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
38 13 2A08 5107 BEQL 50$ ; Branch if acceptable for XVA
2A0A 5108 MSG <-W-CPUREV, CPU rev level limits system space to 1 Gb>
2A42 5109
5A42'CF 89 2A42 5110 50$: BISB3 W^XVA_XMI_REV,- ; Check for XMI adapter rev
50 5A3E'CF 2A46 5111 W^XPA_XMI_REV,R0 ; (Check both XVA & XPA here)
40 13 2A4A 5112 BEQL 60$ ; Branch if acceptable for XVA
2A4C 5113 MSG <-W-XMIREV, XMI adapter rev level limits system space to 1 Gb>
2A8C 5114
5A3F'CF 95 2A8C 5115 60$: TSTB W^XPA_OLD_BI_DEV ; Old BI device prevent XPA (and XVA)?
3A 13 2A90 5116 BEQL 70$ ; Nope
2A92 5117 MSG <-W-OLDBIDEV, old BI device limits system space to 1 Gb>
2ACC 5118
5A3C'CF 95 2ACC 5119 70$: TSTB W^XPA_PREVENTED ; Use of XPA prevented?
16 12 2AD0 5120 BNEQ 90$ ; If so, can't use XVA
5A40'CF 95 2AD2 5121 TSTB W^XVA_PREVENTED ; Some XVA test fail?
10 12 2AD6 5122 BNEQ 90$ ; Sorry
00400000 8F 54 D1 2AD8 5123 CMPL R4,#<1@VA$S_SVPN> ; Past end of extension area?
07 1E 2ADF 5124 BGEQU 90$ ; Yes, nothing else we can do
08 88 2AE1 5125 BISB #RPB$M_EXT_MEM,- ; Fake like an XPA system to force use
00A3 CB 2AE3 5126 RPB$B_FLAGS(R11) ; of XBI+ map registers on BI devices
3D 11 2AE6 5127 BRB 100$ ; Continue
2AE8 5128
2AE8 5129 90$: MSG <-F-VASOVF, system virtual address space limit exceeded>
00 2B22 5130 95$: HALT
FD 11 2B23 5131 BRB 95$ ; Go no further
2B25 5132 ;
2B25 5133 ; The SPT size has been determined and validated. Proceed to build up system space.
2B25 5134 ;
54 54 F9 8F 78 2B25 5135 100$: ASHL #-<VA$V_VPG-2>,R4,R4 ; Page count for SPT allocation
571B'CF 54 D0 2B2A 5136 MOVL R4,W^BOO$GL_SPTPAGCT ; Save count of pages
2B2F 5137
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 131
X-62 + ALLOCSPT - Allocate space for SPT an 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
2B2F 5139 .SBTTL + ALLOCSPT - Allocate space for SPT and SYSPHD
2B2F 5140
2B2F 5141 ALLOCSPT: ; Allocate space for SYSPHD and SPT
2B2F 5142 .ENABLE LSB
58 572B'CF 54 C1 2B2F 5143 ADDL3 R4,W^BOO$GL_SYSPHDPG,R8 ; Total size of PHD+SPT
58 59EC'CF C0 2B35 5144 ADDL W^SCBPAGCT,R8 ; plus SCB
57 48 AB D0 2B3A 5145 MOVL RPB$Q_PFNMAP+4(R11),R7 ; Get address for PFNMAP
03 E0 2B3E 5146 BBS #RPB$V_EXT_MEM,- ; Load the SPT at the 511.5Mb mark if
07 00A3 CB 2B40 5147 RPB$B_FLAGS(R11),5$ ; more than 512Mb
56 5A6B'CF D0 2B44 5148 MOVL W^MEM_HI_PFN,R6 ; Get highest PFN+1 in memory
16 11 2B49 5149 BRB 6$
56 0000'CF 01 C1 2B4B 5150 5$: ADDL3 #1,W^MMG$GL_MAXMEM,R6 ; Get highest usable PFN+1
000FFC00 8F 56 D1 2B51 5151 CMPL R6,#PGS_511.5MB ; More than 511.5 Mb of memory?
07 15 2B58 5152 BLEQ 6$ ; No
56 000FFC00 8F D0 2B5A 5153 MOVL #PGS_511.5MB,R6 ; End SPT at 511.5 Mb (BVP restriction)
2B61 5154
0000'CF 56 D0 2B61 5155 6$: MOVL R6,W^BOO$GL_EXEC_HI_PFN ; Set Hi res. exec PFN delimiter
0000'CF D7 2B66 5156 DECL W^BOO$GL_EXEC_HI_PFN ; PFNs start at 0, not 1
2B6A 5157
56 D7 2B6A 5158 10$: DECL R6 ; Point to next/highest page
27 14 2B6C 5159 BGTR 20$ ; Continue if pages available
2B6E 5160 15$: MSG <-F-Unable to allocate SPT+PHD+SCB.>
00 2B94 5161 HALT ; *** FATAL ERROR ***
2B95 5162
D1 67 56 E1 2B95 5163 20$: BBC R6,(R7),10$ ; Find highest page number
2B99 5164
2B99 5165 ;Because we need a run of physically contiguous pages for the SPT, it may start
2B99 5166 ;further down than our initial point if a bad page is found. Therefore,
2B99 5167 ;BOO$GL_NEXTPFN is left at the initial starting pt. so ALLOCPFN can consume the
2B99 5168 ;higher PFNs in front of (behind?) the bad page(s).
2B99 5169
0000'CF D5 2B99 5170 TSTL W^BOO$GL_NEXTPFN ; Have we marked it?
05 12 2B9D 5171 BNEQ 25$ ; Yes
0000'CF 56 D0 2B9F 5172 MOVL R6,W^BOO$GL_NEXTPFN ; Save High Water mark
50 D4 2BA4 5173 25$: CLRL R0 ; Init count of contiguous pages
06 11 2BA6 5174 BRB 35$ ;
56 D7 2BA8 5175 30$: DECL R6 ; Next page (lower)
BC 67 56 E1 2BAA 5176 BBC R6,(R7),10$ ; Skip if no fit
50 D6 2BAE 5177 35$: INCL R0 ; Bump count of pages
58 50 D1 2BB0 5178 CMPL R0,R8 ; Check for fit
F3 19 2BB3 5179 BLSS 30$ ; Not yet
4C AB 50 C2 2BB5 5180 SUBL R0,RPB$L_PFNCNT(R11) ; Account for pages removed
51 56 D0 2BB9 5181 MOVL R6,R1 ; Copy lowest page number
02 67 51 E5 2BBC 5182 40$: BBCC R1,(R7),50$ ; Mark page allocated
51 D6 2BC0 5183 INCL R1 ; Next page
F7 50 F5 2BC2 5184 50$: SOBGTR R0,40$ ; Allocate them all
2BC5 5185 ;
2BC5 5186 ; R6 - PFN for start of SCB
2BC5 5187 ; R7 - Base of PFNMAP
2BC5 5188 ; R8 - Size of SYSPHD+SPT+SCB in pages
2BC5 5189 ; R4 - SPT size in pages
2BC5 5190 ;
59 56 09 78 2BC5 5191 ASHL #VA$V_VPG,R6,R9 ; Compute physical address of SCB
5706'CF 59 D1 2BC9 5192 CMPL R9,W^BOO$GL_FREEMEM ; Check for overlap with SYSBOOT
9E 19 2BCE 5193 BLSS 15$ ; Continue if OK
5A73'CF 56 D1 2BD0 5194 CMPL R6,W^PFNMAP_HI_PFN ; Ran into PFN Bitmap?
97 15 2BD5 5195 BLEQ 15$ ; Branch if Yes
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 132
X-62 + ALLOCSPT - Allocate space for SPT an 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
5A6F'CF 56 D1 2BD7 5196 CMPL R6,W^CACHE_HI_PFN ; Ran into FIL$OPENFILE Cache?
08 14 2BDC 5197 BGTR 55$ ; Branch if not
5691'CF 7C 2BDE 5198 CLRQ W^FIL$GQ_CACHE ; Yes, disable it
5A6F'CF D4 2BE2 5199 CLRL W^CACHE_HI_PFN
5B1F'CF 56 D1 2BE6 5200 55$: CMPL R6,W^CI_HI_PFN ; Ran into CI Microcode?
2B 14 2BEB 5201 BGTR 57$ ; Branch if not
2BED 5202 BUMP_CI:MSG <-F-PFN allocation overwrites CI ucode.>
00 2C17 5203 HALT
2C18 5204
50 59 D0 2C18 5205 57$: MOVL R9,R0 ; Get a working copy of address
51 58 05 78 2C1B 5206 ASHL #5,R8,R1 ; Get a count of double quadwords
80 7C 2C1F 5207 60$: CLRQ (R0)+ ; Clear a
80 7C 2C21 5208 CLRQ (R0)+ ; double quadword
F9 51 F5 2C23 5209 SOBGTR R1,60$ ; Clear them all
2C26 5210
2C26 5211 .DISABLE LSB
2C26 5212
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 133
X-62 + INIT_SCB - Initialize SCB 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
2C26 5214 .SBTTL + INIT_SCB - Initialize SCB
2C26 5215
2C26 5216 INIT_SCB: ; Initialize system SCB
59F4'CF 59 D0 2C26 5217 MOVL R9,W^SCBPHADDR ; Save physical addr of SCB
69 0000'CF 0200 8F 28 2C2B 5218 MOVC3 #512,W^SCB$AL_BASE,(R9) ; Copy architectural part
2C33 5219 ; of SCB (1 Pg) from template
2C33 5220 ; to system copy. (Returns
2C33 5221 ; SCB Addr+512 in R3.)
50 59F0'CF 00000200 8F C3 2C33 5222 SUBL3 #512,W^SCBBYTCT,R0 ; Get # bytes remaining in SCB
0F 15 2C3D 5223 BLEQ 20$ ; Branch if none
50 50 FE 8F 78 2C3F 5224 ASHL #-2,R0,R0 ; Convert # bytes into longwds
83 00000001'8F D0 2C44 5225 10$: MOVL #ERL$UNEXP+1,(R3)+ ; Set next vector to Unexpected Int
F6 50 F5 2C4B 5226 SOBGTR R0,10$ ; Branch if more vectors
2C4E 5227 ;
2C4E 5228 ; CPU specific code for 11/780. Point SCB vector 0 interrupts and NEXUS
2C4E 5229 ; vector 0 interrupts to separate routine in module ERRORLOG.
2C4E 5230 ;
2C4E 5231
2C4E 5232 .list meb
2C4E 5233 20$: CPUDISP <<780,SCB_VEC_780>,- ; Dispatch on CPU type
2C4E 5234 <750,SCB_VEC_750>,-
2C4E 5235 <730,SCB_VEC_730>,-
2C4E 5236 <790,SCB_VEC_790>,-
2C4E 5237 <UV1,SCB_VEC_UV1>,-
2C4E 5238 <UV,SCB_VEC_UV>,-
2C4E 5239 <420,SCB_VEC_420>,-
2C4E 5240 <520,SCB_VEC_520>,-
2C4E 5241 <550,SCB_VEC_520>,-
2C4E 5242 <600,SCB_VEC_600>,-
2C4E 5243 <650,SCB_VEC_650>,-
2C4E 5244 <670,SCB_VEC_670>,-
2C4E 5245 <660,SCB_VEC_660>,-
2C4E 5246 <690,SCB_VEC_690>,-
2C4E 5247 <700,SCB_VEC_700>,-
2C4E 5248 <8SS,SCB_VEC_8SS>,-
2C4E 5249 <8NN,SCB_VEC_8NN>,-
2C4E 5250 <8PS,SCB_VEC_8PS>,-
2C4E 5251 <009,SCB_VEC_009>,-
2C4E 5252 <9AQ,SCB_VEC_9AQ>,-
2C4E 5253 <9CC,SCB_VEC_9CC>,-
2C4E 5254 <9RR,SCB_VEC_9RR>,-
2C4E 5255 <1202,SCB_VEC_1202>,-
2C4E 5256 <1302,SCB_VEC_1302>,-
2C4E 5257 <1701,SCB_VEC_1701>,-
2C4E 5258 <60, SCB_VEC_60>,-
2C4E 5259 <43, SCB_VEC_43>,-
2C4E 5260 <440,SCB_VEC_440>,-
2C4E 5261 <46, SCB_VEC_46>,-
2C4E 5262 <4A, SCB_VEC_4A>,-
2C4E 5263 <49, SCB_VEC_49>,-
2C4E 5264 <1303,SCB_VEC_1303>,-
2C4E 5265 >,-
2C4E 5266 ENVIRON=VMB,CONTINUE=YES
16 01 00000000'GF 8F 2C4E CASEB G^EXE$GB_CPUTYPE,#$$BASE,#$$LIMIT
2C56 30647$:
0111' 2C56 .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_780-30647$
0146' 2C58 .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_750-30647$
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 134
X-62 + INIT_SCB - Initialize SCB 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
0146' 2C5A .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_730-30647$
0100' 2C5C .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_790-30647$
0105' 2C5E .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_8SS-30647$
00F4' 2C60 .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_8NN-30647$
0146' 2C62 .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_UV1-30647$
0031' 2C64 .IIF EQ $$GENSW, .SIGNED_WORD 30575$-30647$
0146' 2C66 .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_009-30647$
0037' 2C68 .IIF EQ $$GENSW, .SIGNED_WORD 30576$-30647$
0050' 2C6A .IIF EQ $$GENSW, .SIGNED_WORD 30577$-30647$
002E 2C6C .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
002E 2C6E .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
00B1' 2C70 .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_9AQ-30647$
002E 2C72 .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
002E 2C74 .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
00E8' 2C76 .IIF EQ $$GENSW, .SIGNED_WORD SCB_VEC_8PS-30647$
0063' 2C78 .IIF EQ $$GENSW, .SIGNED_WORD 30578$-30647$
0074' 2C7A .IIF EQ $$GENSW, .SIGNED_WORD 30579$-30647$
008B' 2C7C .IIF EQ $$GENSW, .SIGNED_WORD 30580$-30647$
002E 2C7E .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
002E 2C80 .IIF EQ $$GENSW, .WORD 2*<$$LIMIT+1>
00A4' 2C82 .IIF EQ $$GENSW, .SIGNED_WORD 30581$-30647$
007D 31 2C84 BRW 30582$
2C87 30575$:
2C87 30648$:
0112 31 2C87 BRW SCB_VEC_UV
0077 31 2C8A BRW 30582$
2C8D 30576$:
06 01 0000000F'GF 8F 2C8D CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
2C95 30649$:
0107' 2C95 .SIGNED_WORD SCB_VEC_650-30649$
009B' 2C97 .SIGNED_WORD SCB_VEC_9CC-30649$
0107' 2C99 .SIGNED_WORD SCB_VEC_60-30649$
0107' 2C9B .SIGNED_WORD SCB_VEC_420-30649$
000E 2C9D .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
000E 2C9F .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
0107' 2CA1 .SIGNED_WORD SCB_VEC_520-30649$
005E 31 2CA3 BRW 30582$
2CA6 30577$:
03 01 0000000F'GF 8F 2CA6 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
2CAE 30650$:
00EE' 2CAE .SIGNED_WORD SCB_VEC_670-30650$
0082' 2CB0 .SIGNED_WORD SCB_VEC_9RR-30650$
0008 2CB2 .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
00EE' 2CB4 .SIGNED_WORD SCB_VEC_43-30650$
004B 31 2CB6 BRW 30582$
2CB9 30578$:
02 02 0000000F'GF 8F 2CB9 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
2CC1 30651$:
006F' 2CC1 .SIGNED_WORD SCB_VEC_1202-30651$
0006 2CC3 .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
00DB' 2CC5 .SIGNED_WORD SCB_VEC_46-30651$
003A 31 2CC7 BRW 30582$
2CCA 30579$:
05 01 0000000F'GF 8F 2CCA CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
2CD2 30652$:
00CA' 2CD2 .SIGNED_WORD SCB_VEC_690-30652$
005E' 2CD4 .SIGNED_WORD SCB_VEC_1302-30652$
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 135
X-62 + INIT_SCB - Initialize SCB 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
00CA' 2CD6 .SIGNED_WORD SCB_VEC_1303-30652$
00CA' 2CD8 .SIGNED_WORD SCB_VEC_49-30652$
00CA' 2CDA .SIGNED_WORD SCB_VEC_700-30652$
00CA' 2CDC .SIGNED_WORD SCB_VEC_600-30652$
0023 31 2CDE BRW 30582$
2CE1 30580$:
06 01 0000000F'GF 8F 2CE1 CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
2CE9 30653$:
00B3' 2CE9 .SIGNED_WORD SCB_VEC_660-30653$
000E 2CEB .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
000E 2CED .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
00B3' 2CEF .SIGNED_WORD SCB_VEC_440-30653$
00B3' 2CF1 .SIGNED_WORD SCB_VEC_4A-30653$
000E 2CF3 .IIF EQ $$SUBGENSW, .WORD 2*<$$SUBLIMIT+1>
00B3' 2CF5 .SIGNED_WORD SCB_VEC_520-30653$
000A 31 2CF7 BRW 30582$
2CFA 30581$:
00 01 0000000F'GF 8F 2CFA CASEB G^EXE$GB_CPUDATA+15,#$$SUBBASE,#$$SUBLIMIT
2D02 30654$:
002E' 2D02 .SIGNED_WORD SCB_VEC_1701-30654$
2D04 30582$:
2D04 5267 .nlist meb
0095 31 2D04 5268 BRW SCB_VEC_END ; Default action if unknown CPU type
2D07 5269
2D07 5270 SCB_VEC_9AQ: ; Need to fill in SCB pages for all XJAs
51 0109 CB 9A 2D07 5271 MOVZBL RPB$B_SCBPAGCT(R11),R1 ; # of pages in SCB.
69 00000001'9F DE 2D0C 5272 MOVAL @#ERL$VEC_RETURN+1,(R9) ; Dispatches through SCB location 0
2D13 5273 ; should be harmless on 9AQ
0200 C9 00000001'9F DE 2D13 5274 MOVAL @#ERL$VEC_RETURN+1,^X200(R9) ; Ditto for each XJA's SCB page
0400 C9 00000001'9F DE 2D1C 5275 MOVAL @#ERL$VEC_RETURN+1,^X400(R9)
0600 C9 00000001'9F DE 2D25 5276 MOVAL @#ERL$VEC_RETURN+1,^X600(R9)
41 11 2D2E 5277 BRB FILL_NEXUS0 ; Set address in nexus 0 vectors
2D30 5278
2D30 5279 SCB_VEC_9CC: ;
2D30 5280 SCB_VEC_9RR: ; Passive release on Calypso/Rigel
2D30 5281 SCB_VEC_1202:
2D30 5282 SCB_VEC_1302:
2D30 5283 SCB_VEC_1701:
51 0109 CB 9A 2D30 5284 MOVZBL RPB$B_SCBPAGCT(R11),R1 ; # of pages in SCB.
69 00000001'9F DE 2D35 5285 MOVAL @#ERL$VEC_RETURN+1,(R9) ; Dispatches through SCB location 0
2D3C 5286 ; should be harmless on 9CC.
33 11 2D3C 5287 BRB FILL_NEXUS0 ; Set address in nexus 0 vectors
2D3E 5288
2D3E 5289 SCB_VEC_8PS: ;
51 20 D0 2D3E 5290 MOVL #32,R1 ; 32 pages of SCB vectors.
69 00000001'9F DE 2D41 5291 MOVAL @#ERL$VEC_RETURN+1,(R9) ; Dispatches through SCB location 0
2D48 5292 ; should be harmless on 8PS.
27 11 2D48 5293 BRB FILL_NEXUS0 ; Set address in nexus 0 vectors
2D4A 5294
2D4A 5295 SCB_VEC_8NN: ;
51 20 D0 2D4A 5296 MOVL #32,R1 ; 32 pages of SCB vectors.
69 00000001'9F DE 2D4D 5297 MOVAL @#ERL$VEC_RETURN+1,(R9) ; Dispatches through SCB location 0
2D54 5298 ; should be harmless on 8NNN.
1B 11 2D54 5299 BRB FILL_NEXUS0 ; Set address in nexus 0 vectors
2D56 5300
2D56 5301 SCB_VEC_790:
51 04 D0 2D56 5302 MOVL #4,R1 ; 4 pages of SCB vectors
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 136
X-62 + INIT_SCB - Initialize SCB 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
16 11 2D59 5303 BRB FILL_NEXUS0 ; Set address in nexus 0 vectors
2D5B 5304
2D5B 5305 SCB_VEC_8SS: ; Passive release on Scorpio.
51 01 D0 2D5B 5306 MOVL #1,R1 ; 1 page of SCB vectors
69 00000001'9F DE 2D5E 5307 MOVAL @#ERL$VEC_RETURN+1,(R9) ; Dispatches through SCB location 0
0A 11 2D65 5308 BRB FILL_NEXUS0 ; Set address in nexus 0 vectors
2D67 5309
2D67 5310 ;
2D67 5311 ; The passive release interrupt vector (SCB location 0) for the 780 must
2D67 5312 ; specify the kernel stack because this processor can generate a passive
2D67 5313 ; release at IPL 0 (which is illegal when servicing on the interrupt stack).
2D67 5314 ;
2D67 5315 SCB_VEC_780:
51 01 D0 2D67 5316 MOVL #1,R1 ; 1 page of SCB vectors
69 00000000'9F DE 2D6A 5317 MOVAL @#ERL$VEC_RETURN,(R9) ; Dispatches through SCB location 0
2D71 5318 ; should be harmless on a 780 and 8SS.
2D71 5319 FILL_NEXUS0:
50 59 D0 2D71 5320 MOVL R9,R0 ; Copy pointer to SCB
0100 C0 00000001'9F DE 2D74 5321 10$: MOVAL @#ERL$VEC_RETURN+1,^X100(R0) ; Unibus passive releases can cause
0140 C0 0100 C0 D0 2D7D 5322 MOVL ^X100(R0),^X140(R0) ; interrupts for "TR #0"; make them
0180 C0 0100 C0 D0 2D84 5323 MOVL ^X100(R0),^X180(R0) ; harmless (at all 4 IPLs).
01C0 C0 0100 C0 D0 2D8B 5324 MOVL ^X100(R0),^X1C0(R0)
50 00000200 8F C0 2D92 5325 ADDL #^X200,R0 ; Step to next page of SCB
D8 51 F5 2D99 5326 SOBGTR R1,10$ ; Fill in vectors in next SCB page
2D9C 5327
2D9C 5328 SCB_VEC_750:
2D9C 5329 SCB_VEC_730: ; Do nothing for 11/750, 11/730,
2D9C 5330 SCB_VEC_UV1: ; MicroVAX I, or MicroVAX II.
2D9C 5331 SCB_VEC_UV:
2D9C 5332 SCB_VEC_600:
2D9C 5333 SCB_VEC_650:
2D9C 5334 SCB_VEC_670:
2D9C 5335 SCB_VEC_660:
2D9C 5336 SCB_VEC_690:
2D9C 5337 SCB_VEC_700:
2D9C 5338 SCB_VEC_420:
2D9C 5339 SCB_VEC_43:
2D9C 5340 SCB_VEC_440:
2D9C 5341 SCB_VEC_46:
2D9C 5342 SCB_VEC_4A:
2D9C 5343 SCB_VEC_49:
2D9C 5344 SCB_VEC_60:
2D9C 5345 SCB_VEC_009:
2D9C 5346 SCB_VEC_520:
2D9C 5347 SCB_VEC_1303:
2D9C 5348 SCB_VEC_END:
2D9C 5349
2D9C 5350 ; End of CPU dependent code
2D9C 5351
2D9C 5352
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 137
X-62 + INIT_SYSPHD - Initialize SYSPHD 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
2D9C 5354 .SBTTL + INIT_SYSPHD - Initialize SYSPHD
2D9C 5355
2D9C 5356
2D9C 5357 INIT_SYSPHD: ; Initialize System PHD
59 59F0'CF C0 2D9C 5358 ADDL W^SCBBYTCT,R9 ; Step past SCB to PHD
5727'CF 59 D0 2DA1 5359 MOVL R9,W^BOO$GL_SYSPHD ; Save physical PHD address
019C 8F 28 2DA6 5360 MOVC3 #PHD$C_LENGTH,- ; Copy PHD to real place
69 0000'CF 2DAA 5361 W^BOO$A_SYSPHD,(R9)
50 0000'CF D0 2DAE 5362 MOVL W^SGN$GL_SYSDWSCT,R0 ; Get size of System Working Set
00C4 C9 50 D0 2DB3 5363 MOVL R0,PHD$L_WSSIZE(R9) ; Set System Working Set size
50 18 A9 C0 2DB8 5364 ADDL PHD$L_WSNEXT(R9),R0 ; Get pointer to Working Set
1C A9 50 D0 2DBC 5365 MOVL R0,PHD$L_WSLAST(R9) ; Set end of Syste Working Set list
0088 C9 50 D0 2DC0 5366 MOVL R0,PHD$L_WSQUOTA(R9) ; Set Quota values
0100 C9 50 D0 2DC5 5367 MOVL R0,PHD$L_WSAUTH(R9) ; for consistency
008C C9 50 D0 2DCA 5368 MOVL R0,PHD$L_DFWSCNT(R9) ; sake.
0084 C9 50 D0 2DCF 5369 MOVL R0,PHD$L_WSEXTENT(R9) ; ...
0104 C9 50 D0 2DD4 5370 MOVL R0,PHD$L_WSAUTHEXT(R9) ; ...
0000'CF B0 2DD9 5371 MOVW W^SGN$GL_BALSETCT,- ; Set header number
00B6 C9 2DDD 5372 PHD$W_PHVINDEX(R9)
2DE0 5373
50 0000'CF 01 A1 2DE0 5374 ADDW3 #1,W^SGN$GW_SWPFILES,R0 ; Compute 1st SYSTEM page file index
0093 C9 50 90 2DE6 5375 MOVB R0,PHD$B_PAGFIL(R9) ; Assign current SYSTEM page file
00FC C9 50 90 2DEB 5376 MOVB R0,PHD$B_PRCPGFL(R9) ; Equate to PROCESS page file #0
00DB C9 01 90 2DF0 5377 MOVB #1,PHD$B_PGFLCNT(R9) ; Show 1 page file assigned
2DF5 5378
2DF5 5379 ASSUME <PHD$S_PRCPGFLREFS/4> - ; Ensure that page file accounting
2DF5 5380 EQ <1@PTE$S_PRCPGFLX> ; works correctly
2DF5 5381
50 0160 C9 DE 2DF5 5382 MOVAL PHD$L_PRCPGFLREFS(R9),R0 ; Init process page file ref counts
51 00100000 8F D0 2DFA 5383 MOVL #<1@PTE$S_PGFLVBN>,R1
2E01 5384 .REPT <PHD$S_PRCPGFLREFS/4>
2E01 5385 MOVL R1,(R0)+
80 51 D0 2E01 5386 .ENDR
2E0D 5387
2E0D 5388 ASSUME PHD$W_PRCPGFLOPAGES EQ PHD$W_PRCPGFLPAGES+2
00000000'8F D0 2E0D 5389 MOVL #<<MMG$K_PAGE_CHUNK @16> ! MMG$K_PAGE_CHUNK>,-
00F8 C9 2E13 5390 PHD$W_PRCPGFLPAGES(R9) ; Reserve an initial chunk of pages
2E16 5391 ;
2E16 5392 ; NOTE -- Later (in BOO$INITPAGFIL), when the first pagefile is installed, the above
2E16 5393 ; two reservation fields will be adjusted and PFL$L_RSRVPAGCNT will be updated.
2E16 5394
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 138
X-62 + INIT_PPGFLVA - Establish initial val 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
2E16 5396 .SBTTL + INIT_PPGFLVA - Establish initial values for PPGFLVA
2E16 5397
2E16 5398 ;
2E16 5399 ; Establish initial value for PPGFLVA in the system PHD. This field contains
2E16 5400 ; the number of remaining pages that can be safely mapped with page file backing
2E16 5401 ; store. For normal processes, it is established by the code that assigns
2E16 5402 ; and deassigns process pagefiles, and the code that creates and deletes
2E16 5403 ; virtual address space. Since the assignment of the 1st process pagefile for
2E16 5404 ; the system "process" cannot be done with MMG$ASNPRCPGFL, and VA is created
2E16 5405 ; using special mechanisms at boot time, the initial value must be calculated
2E16 5406 ; here.
2E16 5407 ;
2E16 5408 ; The pieces of system space requiring page file backing store that must be
2E16 5409 ; accounted for here are:
2E16 5410 ;
2E16 5411 ; Paged dynamic memory (SGN$GL_PAGEDYN bytes, known to be multiple of 512)
2E16 5412 ; Global page table entries (BOO$GL_GPTPGCT pages)
2E16 5413 ;
2E16 5414 ; Pageable data areas in loadable images are accounted for by the routines
2E16 5415 ; in the modules SYSLDR and LOADSUB.
2E16 5416 ;
50 0000'CF F7 8F 78 2E16 5417 ASHL #-VA$V_VPG,W^SGN$GL_PAGEDYN,R0 ; Convert paged pool byte count to pages
51 00100000 8F 50 C3 2E1D 5418 SUBL3 R0,#<1@PTE$S_PGFLVBN>,R1 ; Debit mappable page count for pool
0170 C9 51 5717'CF C3 2E25 5419 SUBL3 W^BOO$GL_GPTPGCT,R1,- ; Likewise for GPT pages
2E2D 5420 PHD$L_PPGFLVA(R9)
2C 18 2E2D 5421 BGEQ 5$
2E2F 5422 MSG <-F-Pageable system space exceeds 512 MB>
00 2E5A 5423 HALT
2E5B 5424
2E5B 5425 5$:
74 A9 571B'CF 07 78 2E5B 5426 ASHL #<VA$V_VPG-2>,W^BOO$GL_SPTPAGCT,PHD$L_P0LRASTL(R9) ; Set SPT length
0000'CF 74 A9 D0 2E62 5427 MOVL PHD$L_P0LRASTL(R9),W^MMG$GL_SPTLEN ; and save for reference
51 572B'CF 09 78 2E68 5428 ASHL #VA$V_VPG,W^BOO$GL_SYSPHDPG,R1 ; Byte offset to SPT
0000'CF 59 51 C1 2E6E 5429 ADDL3 R1,R9,W^MMG$GL_SBR ; Save physical addr of SPT
0000'CF 0000'CF D0 2E74 5430 MOVL W^MMG$GL_SBR,W^LDR$GL_SPTBASE ; Save it for loader
0094 C9 572B'CF 09 78 2E7B 5431 ASHL #VA$V_VPG,W^BOO$GL_SYSPHDPG,PHD$L_PSTBASOFF(R9) ; Save as byte offset
50 74 A9 09 78 2E83 5432 ASHL #VA$V_VPG,PHD$L_P0LRASTL(R9),R0 ; Compute Max System Address+1
52 01 1F 78 2E88 5433 ASHL #VA$V_SYSTEM,#1,R2 ; System mask
009C C9 50 52 C9 2E8C 5434 BISL3 R2,R0,PHD$L_FREP0VA(R9) ; Save as Max Address
0000'CF 50 52 C9 2E92 5435 BISL3 R2,R0,W^MMG$GL_FRESVA ;
0000'CF 50 52 C9 2E98 5436 BISL3 R2,R0,W^MMG$GL_MAXSYSVA ;
51 74 A9 20 C3 2E9E 5437 SUBL3 #CPU$C_MAX_CPUS,PHD$L_P0LRASTL(R9),R1 ; VPN of P0PT Maps
50 51 09 78 2EA3 5438 ASHL #VA$V_VPG,R1,R0 ; Convert to byte address
5A2C'CF 50 52 C9 2EA7 5439 BISL3 R2,R0,W^BOO_P0PT_MAP ; Save VA of P0PT Map base
0000'CF 50 52 C9 2EAD 5440 BISL3 R2,R0,W^MMG$GL_MAXGPTE ; Save VA past last GPTE
51 5717'CF C2 2EB3 5441 SUBL W^BOO$GL_GPTPGCT,R1 ; VPN of GPT
50 51 09 78 2EB8 5442 ASHL #VA$V_VPG,R1,R0 ; Convert to byte address
0000'CF 50 52 C9 2EBC 5443 BISL3 R2,R0,W^MMG$GL_GPTE ; Base of Global Page Table Entries
0000'CF 50 52 C9 2EC2 5444 BISL3 R2,R0,W^MMG$GL_GPTBASE ; Save as GPT base
51 571B'CF C2 2EC8 5445 SUBL W^BOO$GL_SPTPAGCT,R1 ; VPN of SPT
50 51 09 78 2ECD 5446 ASHL #VA$V_VPG,R1,R0 ; Bytes address
0000'CF 50 52 C9 2ED1 5447 BISL3 R2,R0,W^MMG$GL_SPTBASE ; Save as SPT base
70 A9 50 52 C9 2ED7 5448 BISL3 R2,R0,PHD$L_P0BR(R9) ; and Virtual SBR
51 572B'CF C2 2EDC 5449 SUBL W^BOO$GL_SYSPHDPG,R1 ; VPN of SYSPHD
50 51 09 78 2EE1 5450 ASHL #VA$V_VPG,R1,R0 ; Byte address
0000'CF 50 52 C9 2EE5 5451 BISL3 R2,R0,W^MMG$GL_SYSPHD ; Save virtual pointer to PHD
0000'CF 572B'CF 09 78 2EEB 5452 ASHL #VA$V_VPG,W^BOO$GL_SYSPHDPG,W^MMG$GL_SYSPHDLN ; Bytes in System PHD
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 139
X-62 + INIT_PPGFLVA - Establish initial val 8-DEC-1993 20:52:37 [BOOTS.SRC]SYSBOOT.MAR;1 (10)
50 0000'CF 0000'CF C5 2EF3 5453 MULL3 W^SWP$GL_BSLOTSZ,W^SGN$GL_BALSETCT,R0 ; Balance set Map size
50 51 50 C3 2EFB 5454 SUBL3 R0,R1,R0 ; VPN of BAL base
0000'CF 0000'DF40 DE 2EFF 5455 MOVAL @W^MMG$GL_SPTBASE[R0],W^SWP$GL_BALSPT ; Set base of Balance Map
50 50 09 78 2F07 5456 ASHL #VA$V_VPG,R0,R0 ; Convert VPN to VA
0000'CF 50 52 C9 2F0B 5457 BISL3 R2,R0,W^SWP$GL_BALBASE ; Save VA base of balance slots
50 59F0'CF C2 2F11 5458 SUBL W^SCBBYTCT,R0 ; Compute VA of SCB
00000000'EF 50 52 C9 2F16 5459 BISL3 R2,R0,EXE$GL_SCB ; Save system space VA of SCB
2F1E 5460
2F1E 5461
SYSBOOT - VMS Secondary Bootstrap Routine 8-MAR-1994 22:26:51 VAX MACRO V5.4-3 Page 140
| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 350.1 | | EVMS::MORONEY | | Wed Mar 19 1997 19:30 | 8 |
| 240 interrupt stack pages? What are they doing ? (default is 6!)
As a wild guess and without looking, there may be a word counter overflowing
(128 pages * 512 = 64K) Try it with something like intstkpages=129 and see
if you get the same problem. Otherwise get a forced crash and see what the
per CPU databases and PTEs look like.
-Mike
|
| 350.2 | | AUSS::GARSON | DECcharity Program Office | Wed Mar 19 1997 21:36 | 14 |
| re .0
You should escalate this in some manner. SYSGEN says that the maximum
is 65535 pages and if that doesn't work then either it should be made
to or the maximum reduced.
As a random thought, are you changing the parameter with AUTOGEN or
directly in SYSGEN? Obviously AUTOGEN is much preferred. But you might
try it directly in case an overflow is occurring in AUTOGEN. At the
very least if you are changing with AUTOGEN, review the before/after
for SETPARAMS.DAT to see whether anything that was changed in
consequence looks odd. If each CPU has its own interrupt stack, I must
admit that a quick look at AUTOGEN did not reveal how it accounts for
that.
|
| 350.3 | thanks for the comment | GIDDAY::SHCHIU | | Thu Mar 20 1997 18:05 | 2 |
|
|