| Title: | VAX and Alpha VMS |
| Notice: | This is a new VMSnotes, please read note 2.1 |
| Moderator: | VAXAXP::BERNARDO |
| Created: | Wed Jan 22 1997 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 703 |
| Total number of notes: | 3722 |
Hello,
I am investigating the following non fatal SSRVEXCEPT
on a VAX4000-700. The TBSTS register reports a TB parity error,
but there are no machine check enteries in the errorlog.
Is the TB parity error a real error?
Regards,
John Kilroy.
Cross posted in MICROVAX conference.
*********************************************************************
NON-FATAL BUGCHECK KA692-AA CPU Microcode Rev # 2. CONSOLE FW REV#
2.4
Standard Microcode Patch Patch Rev # 1.
SSRVEXCEPT, Unexpected system service exception
PROCESS NAME ERRFMT
PROCESS ID 00010009
ERROR PC 81778FF7
ERROR PSL 01C00000
INTERRUPT PRIORITY LEVEL = 00.
PREVIOUS MODE = USER
CURRENT MODE = EXECUTIVE
FIRST PART DONE CLEAR
STACK POINTERS
KSP 7FFE77B4 ESP 7FFE975C SSP 7FFED800 USP 7FECF564 ISP 84FD3600
GENERAL REGISTERS
R0 01C00009 R1 7FFE9798 R2 00000E00 R3 7FEFF718 R4 7FEFF600
R5 7FFDFE94 R6 00000002 R7 00000003 R8 7FECF5E0 R9 7FEFF608
R10 00000000 R11 7FFDFE70 AP 7FFE9774 FP 7FFE975C SP 7FFE77F8
KA692 REGISTER SUBPACKET
TODR 0000FFFF
BPCR FFFF0000
PAMODE 01F5FFFF
32 BIT PHYSICAL ADDRESS MODE
MUST BE ZERO FIELD NON-ZERO
MMEPTE 00010047
memory management exception PTE
MMESTS 6A008328
MUST BE ZERO FIELD NON-ZERO <13:03
TNV fault
MUST BE ZERO FIELD NON-ZERO <25:16
VALID IBOX SPECIFIER STORED
PCSCR 01000002
MUST BE ZERO FIELD NON-ZERO
Patchable control store disabled
standard microcode patch
CPU microcode Patch Rev # = 1.
ICSR 06B40100
virtual instruction cache disabled
ECR 3D440002
SUBSET INTERVAL TIMER ENABLED
PERFORMANCE MONITR FEEDBACK TEST ENABLE
FBOX STAGE 4 BYPASS DISABLED
MUST BE ZERO FIELD NON-ZERO
TBSTS 00000003
^ LOCK SET
-----------> TRANSLATION BUFFER DATA PARITY ERROR
em_latch invalid
s5 command = 00(X)
valid Ebox reference error stored
PCCTL 00000000
pcache disabled for D-stream
reference
pcache disabled for I-stream
reference
PCACHE PARITY ERROR DETECTION
DISABLED
MUST BE ONE FIELD NON-ONE
PCSTS 00000000
CCTL 00000000
backup cache disabled
bcache tag ram speed:
READ = 3 CYCLES, WRITE = 3 CYCLES
bcache data ram speed:
READ = 2 CYCLES, WRITE = CYCLES
128 kilobyte backup cache
BCEDSTS 00000000
MESR 00000000
MMCDSR 00000000
2600 cycles before disown write
tmeout
disable logging soft errors
CQBIC on CP_I02
CESR 00000000
CMCDSR 00000000
IO2 ID NOT ENABLED
DMA PREFETCHING DISABLED
3200 Cycles Before NDAL Timeout
144 cycles before cp1 mt timeout
144 CYCLES BEFORE CP2 MT TIMEOUT
cp1 interrupts pending:
none
cp2 interrupts pending:
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 286.1 | TURRIS::MICROVAX is the right place... | XDELTA::HOFFMAN | Steve, OpenVMS Engineering | Wed Mar 05 1997 10:38 | 0 |
| 286.2 | Why not a Machine Check? | SIOG::KILROY | Wed Mar 05 1997 11:02 | 10 | |
Steve,
Is there any possibility that VMS is not reporting
the Translation Buffer Parity Error as a Machine check and that
we are then getting a SSRVEXCEPT?
Regards,
John Kilroy.
| |||||
| 286.3 | Assistance In Decoding Needed... | XDELTA::HOFFMAN | Steve, OpenVMS Engineering | Wed Mar 05 1997 11:23 | 12 |
: Is there any possibility that VMS is not reporting : the Translation Buffer Parity Error as a Machine check and that : we are then getting a SSRVEXCEPT? All sorts of strange things can happen with memory and cache errors, and the folks in MICROVAX are much more likely able to decode this error for you. (I've also seen cases where failing disk sectors can cause odd parity and memory errors -- bad bits `under' the page file is one of the classics -- and where rogue device drivers can cause flakey behaviour -- to be detected by higher layers.) | |||||