Conference alfaxp::jobs

1129.0. "JOB: CAD/DVT Verification Engineer" by SUBSYS::OKEEFE () Wed May 21 1997 13:48

      Requester: David O'Keefe
      Recruiter: Marty Dorfman
      Job Title: Hardware Senior Engineer
           Site: Shrewsbury, MA
     Date Req'd: ASAP
          Shift: 1
     Travel (%): <5%

---------------------------------------------------------------------------

JOB DESCRIPTION/RESPONSIBILITIES (work to be done/unique features of this       
position):

This position is for a CAD DVT / Design Senior Engineer to join a ASIC
development team in Shrewsbury, MA. This engineer will lead the ASIC
design verification effort, to minimize errors in the released designs.
This verification effort will require the use of outside vendor asic
libraries and structural models from Verilog designs for the new gate
array. This person will be responsible for a significant portion of the
verification effort, and may have design responsibilities commensurate
with experience. This effort will require close cooperation with the
design team to ensure completeness of verification. This candidate will
be expected to function as both a senior technical team member and also
to plan and coordinate the verification tasks. 

Other responsibilities/tasks will be assigned based on abilities and 
project requirements.

---------------------------------------------------------------------------

EXPERIENCE AND/OR EDUCATIONAL REQUIREMENTS (minimum qualifications):            

A qualified candidate for the CAD DVT position will have significant
knowledge of existing design and verification systems, the verification
process and the CAD tools used. A Good working knowledge of the Verilog,
Viewlogic and the verification process currently being used for ASIC
development is preferred. A good working knowledge of the SCSI bus is
also desired. 

A Bachelors Degree in Computer Science or Electrical Engineering or
equivalent with a minimum of 3 years of hardware development experience.
-------------------------------------------------------------------------------