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| Title: | AlphaServer 4100 |
|
| Moderator: | MOVMON::DAVIS S |
|
| Created: | Tue Apr 16 1996 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 648 |
| Total number of notes: | 3158 |
582.0. "A new machine check...!!!" by PANTER::AUBERT () Wed Apr 30 1997 10:23
Hello,
I have a new machine check on an AlphaServer 4100 which has the same
configuration as the one in note 578.
Any help diagnosing this problem will be appreciated.
Thierry
% dia -R -o full -f binary.errlog.shd50 | more
Event record: 2997 of file: ./binary.errlog.shd50 is corrupted.
Recovering...
DECevent V2.3
******************************** ENTRY 1
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 1.
Timestamp of occurrence 30-APR-1997 00:10:43
Host name shd50
System type register x00000016 AlphaServer 4000 Series
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 300. Start-Up ASCII Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 3. Startup
ASCII Message
Alpha boot: available memory from 0xb12000 to 0xfffe000
Digital UNIX V4.0B (Rev. 564); Tue Feb 25 16:05:17 MET 1997
physical memory = 256.00 megabytes.
available memory = 244.92 megabytes.
using 975 buffers containing 7.61 megabytes of memory
Master cpu at slot 0.
Firmware revision: 3.0
PALcode: Digital-UNIX/OSF version 1.21
AlphaServer 4100 5/300 0MB
pci1 at mcbus0 slot 5
psiop0 at pci1 slot 1
Loading SIOP: script c0000300, reg 4444000, data c000c250
scsi0 at psiop0 slot 0
rz5 at scsi0 target 5 lun 0 (LID=0) (DEC RRD45 (C) DEC 0436)
pza0 at pci1 slot 2
pza0 firmware version: DEC P01 A10
scsi1 at pza0 slot 0
tz8 at scsi1 target 0 lun 0 (LID=1) (STK SD-3 011E)
(Wide16)
pza1 at pci1 slot 3
pza1 firmware version: DEC P01 A10
scsi2 at pza1 slot 0
tz16 at scsi2 target 0 lun 0 (LID=2) (STK SD-3
011E)
(Wide16)
pza2 at pci1 slot 4
pza2 firmware version: DEC P01 A10
scsi3 at pza2 slot 0
tz24 at scsi3 target 0 lun 0 (LID=3) (STK SD-3
011E)
(Wide16)
pza3 at pci1 slot 5
pza3 firmware version: DEC P01 A10
scsi4 at pza3 slot 0
tz32 at scsi4 target 0 lun 0 (LID=4) (STK SD-3
011E)
(Wide16)
gpc0 at eisa0
pci0 at mcbus0 slot 4
eisa0 at pci0
ace0 at eisa0
ace1 at eisa0
lp0 at eisa0
fdi0 at eisa0
fd0 at fdi0 unit 0
pci2000 at pci0 slot 2
isp0 at pci2000 slot 0
isp0: QLOGIC ISP1020A
isp0: Firmware revision 2.10 (loaded by console)
scsi5 at isp0 slot 0
rz40 at scsi5 target 0 lun 0 (LID=5) (DEC RZ29B (C) DEC
0016)
(Wide16)
rz41 at scsi5 target 1 lun 0 (LID=6) (DEC RZ29B (C) DEC
0016)
(Wide16)
rz42 at scsi5 target 2 lun 0 (LID=7) (DEC RZ29B (C) DEC
0016)
(Wide16)
rz43 at scsi5 target 3 lun 0 (LID=8) (DEC RZ29B (C) DEC
0016)
(Wide16)
rz44 at scsi5 target 4 lun 0 (LID=9) (DEC RZ29B (C) DEC
0016)
(Wide16)
rz45 at scsi5 target 5 lun 0 (LID=10) (DEC RZ29B (C) DEC
0016)
(Wide16)
rz46 at scsi5 target 6 lun 0 (LID=11) (DEC RZ29B (C) DEC
0016)
(Wide16)
tu0: DECchip 21140-AA: Revision: 1.2
tu0 at pci0 slot 3
tu0: DEC Fast Ethernet Interface, hardware address:
00-00-F8-31-10-CF
tu0: console mode: selecting 10BaseT (UTP) port: half duplex
hip0: Roadrunner version 2 (20000900)
hip0 at pci0 slot 4
hip0 slot 4: PCI/HIPPI interface 0-a0-88-1-0-72
fta0 DEC DEFPA FDDI Module, Hardware Revision 1
fta0 at pci0 slot 5
fta0: DMA Available.
fta0: DEC DEFPA (PDQ) FDDI Interface, Hardware address:
00-00-F8-4A-8C-BA
fta0: Firmware rev: 2.46
Created FRU table configuration binary errorlog packet
kernel console: ace0
dli: configured
******************************** ENTRY 2
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 0.
Timestamp of occurrence 30-APR-1997 00:10:43
Host name shd50
System type register x00000016 AlphaServer 4000 Series
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 110. Generalized Machine State Type
SWI Minor class 3. System configuration
******************** FRU Table Header ******************
FRU Table Version x00000004 Major Revision 4.
Minor Revision 0.
================ System Resource Subpacket ===============
Length x015D
Class 1. System Resource Subpacket
Type 1. System Platform
Rev 2.
System Variation x0000000000000865
SysType Spec: AlphaServer 4100
Rack
Graphics: NO Embedded
Graphics
Pwr Fail Restart: Restart Primary
Proc
PowerFail: Full Battery
Backup
Console: Embedded Console
MultiProcessing: MultiProcessing
Support
Reset Reason x00000000 Unrecognized Reset Reason
Number Environ Variables 11.
Manufacturer Digital
Model 4100
Serial Number AY65200676
Revision Level A01
Console Type Revision V3.0-10, 19-NOV-1996 13:57:07
Environmental Var 1: auto_action:BOOT
Environmental Var 2: boot_dev:dkf0.0.0.2000.0
Environmental Var 3: bootdef_dev:dkf0.0.0.2000.0
Environmental Var 4: booted_dev:dkf0.0.0.2000.0
Environmental Var 5: boot_file:
Environmental Var 6: booted_file:
Environmental Var 7: boot_osflags:A
Environmental Var 8: booted_osflags:A
Environmental Var 9: boot_reset:OFF
Environmental Var 10: dump_dev:
Environmental Var 11: enable_audit:ON
--------------------- FRU Subpacket ----------------------
Length x0054
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 0. Slot Name: System Motherboard
Self Test Status x00000001 FRU passed Self-Test
Manufacturer Digital
Model 4100
Part Number 23803-01
Serial Number AY64301898
Revision Level A01
Firmware RevLevel * NOT Logged *
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x0061
Class 1. System Resource Subpacket
Type 2. Processor
Rev 3.
Processor ID 0. ID of this Processor in
Multiprocessor Sys
Processor Family x00000030 Alpha AXP
CPU State x00000000000001CC
PA, Processor Available
PP, Processor Present
PV, PALCODE Valid
PMV, PALCODE Memory Valid
PL, PALCODE Loaded
HALTREQ: Default
AVAILABLE PALcode
PALcode Image 1 x0004000200010113
Maximum CPUs 4.
Compatability 2.
PALcode Revision OpenVMS PALcode V1.19
PALcode Image 2 x0004000E00020115
Maximum CPUs 4.
Compatability 14.
PALcode Revision UNIX PALcode V1.21
Processor Type x0000000500000005
EV5 (21164), Pass 4
Processor Variation x0000000000000007
VAX-FP, VAX floating point support
IEEE-FP, IEEE floating point
support
PE, Processor eligible to become
Primary
Manufacturer Digital
Serial Number KA626PWEDE
Revision Level 1
--------------------- FRU Subpacket ----------------------
Length x005A
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 2. Slot Name: CPU0
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 500000005
Part Number B3001-CA
Serial Number KA626PWEDE
Revision Level 1
Firmware RevLevel V1.1
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x0061
Class 1. System Resource Subpacket
Type 2. Processor
Rev 3.
Processor ID 1.
Processor Family x00000030 Alpha AXP
CPU State x00000000000001CC
PA, Processor Available
PP, Processor Present
PV, PALCODE Valid
PMV, PALCODE Memory Valid
PL, PALCODE Loaded
HALTREQ: Default
AVAILABLE PALcode
PALcode Image 1 x0004000200010113
Maximum CPUs 4.
Compatability 2.
PALcode Revision OpenVMS PALcode V1.19
PALcode Image 2 x0004000E00020115
Maximum CPUs 4.
Compatability 14.
PALcode Revision UNIX PALcode V1.21
Processor Type x0000000500000005
EV5 (21164), Pass 4
Processor Variation x0000000000000003
VAX-FP, VAX floating point support
IEEE-FP, IEEE floating point
support
Manufacturer Digital
Serial Number KA629RCWPC
Revision Level 1
--------------------- FRU Subpacket ----------------------
Length x005A
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 3. Slot Name: CPU1
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 500000005
Part Number B3001-CA
Serial Number KA629RCWPC
Revision Level 1
Firmware RevLevel V1.1
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x0061
Class 1. System Resource Subpacket
Type 2. Processor
Rev 3.
Processor ID 2.
Processor Family x00000030 Alpha AXP
CPU State x00000000000001CC
PA, Processor Available
PP, Processor Present
PV, PALCODE Valid
PMV, PALCODE Memory Valid
PL, PALCODE Loaded
HALTREQ: Default
AVAILABLE PALcode
PALcode Image 1 x0004000200010113
Maximum CPUs 4.
Compatability 2.
PALcode Revision OpenVMS PALcode V1.19
PALcode Image 2 x0004000E00020115
Maximum CPUs 4.
Compatability 14.
PALcode Revision UNIX PALcode V1.21
Processor Type x0000000500000005
EV5 (21164), Pass 4
Processor Variation x0000000000000003
VAX-FP, VAX floating point support
IEEE-FP, IEEE floating point
support
Manufacturer Digital
Serial Number KA629RCWMH
Revision Level 1
--------------------- FRU Subpacket ----------------------
Length x005A
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 6. Slot Name: CPU2 (4100) or IOD2/3
(4000)
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 500000005
Part Number B3001-CA
Serial Number KA629RCWMH
Revision Level 1
Firmware RevLevel V1.1
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x0061
Class 1. System Resource Subpacket
Type 2. Processor
Rev 3.
Processor ID 3.
Processor Family x00000030 Alpha AXP
CPU State x00000000000001CC
PA, Processor Available
PP, Processor Present
PV, PALCODE Valid
PMV, PALCODE Memory Valid
PL, PALCODE Loaded
HALTREQ: Default
AVAILABLE PALcode
PALcode Image 1 x0004000200010113
Maximum CPUs 4.
Compatability 2.
PALcode Revision OpenVMS PALcode V1.19
PALcode Image 2 x0004000E00020115
Maximum CPUs 4.
Compatability 14.
PALcode Revision UNIX PALcode V1.21
Processor Type x0000000500000005
EV5 (21164), Pass 4
Processor Variation x0000000000000003
VAX-FP, VAX floating point support
IEEE-FP, IEEE floating point
support
Manufacturer Digital
Serial Number KA628RAKDK
Revision Level 1
--------------------- FRU Subpacket ----------------------
Length x005A
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 7. Slot Name: CPU3 (4100) or IOD2/3
(4000)
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 500000005
Part Number B3001-CA
Serial Number KA628RAKDK
Revision Level 1
Firmware RevLevel V1.1
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x001D
Class 1. System Resource Subpacket
Type 3. Memory
Rev 2.
Total Memory Size x00000100 Mbytes Installed: 256.
Memory Available x00000100 Mbytes Available: 256.
Interleave Mode * NOT Logged *
--------------------- FRU Subpacket ----------------------
Length x0052
Class 2. FRU Subpacket
Type 2. Memory FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 0. Slot Name: MEM0L and MEM0H
Self Test Status x00000001 FRU passed Self-Test
Total Memory Size 128. Mega Bytes (2 Modules)
Module Size 64. Mega Bytes (per Module)
Memory Base Addr x0000000000000000
Memory Module Type x0000000000000003
Syncronous DRAM
Manufacturer Digital
Model * NOT Logged *
Part Number * NOT Logged *
Serial Number * NOT Logged *
Revision Level * NOT Logged *
Firmware RevLevel * NOT Logged *
Self Test Information * NOT Logged *
--------------------- FRU Subpacket ----------------------
Length x0052
Class 2. FRU Subpacket
Type 2. Memory FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 1. Slot Name: MEM1L and MEM1H
Self Test Status x00000001 FRU passed Self-Test
Total Memory Size 128. Mega Bytes (2 Modules)
Module Size 64. Mega Bytes (per Module)
Memory Base Addr x0000000008000000
Memory Module Type x0000000000000003
Syncronous DRAM
Manufacturer Digital
Model * NOT Logged *
Part Number * NOT Logged *
Serial Number * NOT Logged *
Revision Level * NOT Logged *
Firmware RevLevel * NOT Logged *
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x0048
Class 1. System Resource Subpacket
Type 4. System Bus Bridge
Rev 2.
Bridge Level x0001 PRIMARY Sys Bus Bridge: system ->
bus_type
Bus Type x0002 System Bus to PCI Bus Bridge
Num Registers 10.
This Bus Bridge Phy Addr x000000F9E0000000
IOD# 0
Dev Type & Rev Register x06008032 CAP Chip Revision:
x00000002
B3040 Module Revision:
x00000003
B3050 Module Revision:
x00000000
B3050 Module Type: Left Hand
PCI-EISA Bus Bridge Present on PCI
Segment
Device Class: Host Bus to PCI
Bridge
MC-PCI Command Register x42460FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol:
Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data
Transactions
Bridge ACCEPTS 64 Bit Data
Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use RD/MOD/WRT for <64 Byte Block
Mem Wrt
Wrt PEND_NUM Threshold: 6.
RD_TYPE Memory Prefetch Algorithm:
Short
RL_TYPE Mem Rd Line Prefetch Type:
Medium
RM_TYPE Mem Rd Multiple Cmd Type:
Long
ARB_MODE PCI Arbitration: Round
Robin
Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27>
x00000000
IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25>
x00000000
Interrupt Ctrl Register x00000003 Write Device Interrupt Info
Struct:Enabled
Intr Target Dev Register x0000003A Intr Trgt-0 Dev ID(Octal) o72
Intr Trgt-1 Dev ID(Octal) o0
Intr Target Addr Register x00006000 Int Trgt Data Struct Ofst
x00000000
Int Info Mem Trgt Pg Addr
x00000006
Int Trgt Adr Ext Register x00000000 Int Info Mem Upr Adr Bits
x00000000
Interrupt Mask0 Register x00250000
Interrupt Mask1 Register x00000000
================ System Resource Subpacket ===============
Length x00F8
Class 1. System Resource Subpacket
Type 6. EISA
Rev 2.
- ESC Registers - 26.
Revision ID x13 Unrecognized
Mode Select Register x24 PIRQx# Mux/Map Ctrl<2:0>: x04
NMI on SERR(SysErr) Sig Disabled
GPCS[2:0]# Functions Selected
Config RAM Page Adr Gen Enabled
MREQ[7:4]#/PIRQ[3:0]# Disabled
BIOS Chip Select A x1F Low BIOS 1 Enabled
Low BIOS 2 Enabled
Low BIOS 3 Enabled
Low BIOS 4 Enabled
High BIOS Enabled
BIOS Chip Select B x00
EISA Clock Divisor xC8 Clock Divisor = 4 (33.33MHz)
KBFULL Enabled (82374SB Only)
Peripheral Chip Sel A x83 Real Time Clock Decode Enabled
Keyboard Controller Decode Enabled
Floppy/IDE Decode: 0b00
Primary Flpy Addr Rang Enabled
Keyboard Ctlr Mapped to X-Bus
Peripheral Chip Sel B xC4 Serial Port A Adr Decode: 0b00
Serial Port B Adr Decode: 0b01
LPT1 Port Decode Enabled
PORT 92 Decode Enabled
CRAM Decode Enabled
EISA ID Byte 1 x10
EISA ID Byte 2 xA3
EISA ID Byte 3 x64
EISA ID Byte 4 x00
Scatter/Gather Base Addr x00
PIRQ Route CSR-0 x00 IRQ Routing Bits <06:00>:
Reserved IRQx
Routing of Interrupts Enabled
PIRQ Route CSR-1 x00 IRQ Routing Bits <06:00>:
Reserved IRQx
Routing of Interrupts Enabled
PIRQ Route CSR-2 x00 IRQ Routing Bits <06:00>:
Reserved IRQx
Routing of Interrupts Enabled
PIRQ Route CSR-3 x00 IRQ Routing Bits <06:00>:
Reserved IRQx
Routing of Interrupts Enabled
Gen Purp Chip Sel Addr 0 x0530
Gen Purp Chip Sel Mask 0 x01
Gen Purp Chip Sel Addr 1 x0026
Gen Purp Chip Sel Mask 1 x01
Gen Purp Chip Sel Addr 2 xC000
Gen Purp Chip Sel Mask 2 x00
Gen Purp Chip X-Bus Ctrl xFB GPCS 0 XBUSOE# Generates Enabled
GPCS 1 XBUSOE# Generates Enabled
-- PCEB Registers -- 17.
Vendor/Device ID Code x04828086
Vendor: x8086 Intel
Device: x0482 Intel 82375EB ** PCI-to-EISA
BRIDGE **
PCI Command Low <7:0> x00000007 I/O Space Enabled
Memory Space Enabled
Bus Master Enabled
Special Cycle Not Supported
Mem Write Invalidate Not Supported
VGA Palette Snoop Not Supported
Parity Checking Disabled
Wait State Control Not Supported
PCI Command High <15:8> x00000000 SERR# Disabled
Revision ID x00000015
Master Latency Timer x000000F8 Count: 31.
PCI Control x00000060 Slow Sample Point
Interrupt Acknowledge Enabled
EISA-to-PCI Line Buf Enabled
PCI Arbiter Control x0000009D Guaranteed Access Time Mod Enabled
Bus Lock Disbled
Bus Park Enabled
Retries unmasked after 64 PCICLK's
Auto-PEREQ# Control Enabled
PCI Arbiter Priority Ctrl x000000F0 B0PRI = PCEBREQ# > REQ0#
B1PRI = CPUREQ# > REQ3#
B2PRI = Bank0 > Bank3 > Bank1
Bank 0 Rotate Control Enabled
Bank 1 Rotate Control Enabled
Bank 2 Rotate Control Enabled
Bank 3 Rotate Control Enabled
PCI Decode Control x00000020 Subtractive Decode (82375SB Only)
IDEDC Positive Decode Disabled
8259C Positive Decode Enabled
EISA-to-PCI Mem Attribute x00000001 Region 1 Buffered Access
Region 2 Non-Buffered Access
Region 3 Non-Buffered Access
Region 4 Non-Buffered Access
Mem Region 1 Addr <7:0> x00000000
Mem Region 1 Addr <15:8> x00000000
Mem Region 1 Addr <23:16> x000000FF
Mem Region 1 Addr <31:24> x000000FF
Number of EISA Devices - 4.
** Platform/Configuration Specific EISA SLOT Identification
Slot 1. ** Device NOT Present
Slot 2. ** Device NOT Present
Slot 3. ** Device NOT Present
Slot 4. ** Device NOT Present
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000F9C0010018
PCI: 0
Bus: 0
Device Number: 1
Vendor/Device ID Code x04828086
Vendor: x8086 Intel
Device: x0482 Intel 82375EB ** PCI-to-EISA
BRIDGE **
Command Register x0007 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
*IGNORE*
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
DISABLED
Fast Back-to-Back to Many Target:
DISABLED
Status Register x0200 Device is 33 Mhz Capable.
No Support for User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Not Supported in Target
Device.
Device Select Timing: Medium.
Device Revision x15
Device Class Code x000000 Zero's: Undefined or No Class Code
Support
Sys Cache Line Size x00
Latency Timer Value xF8
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00000000
Base Address Register 2 x00000000
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x00
Interrupt Pin Being Used x00
Min Bus Grant/Burst x00
Max Bus Latency x00
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Bridge Registers ----
PCI Configuration Addr x000000F9C0020018
PCI: 0
Bus: 0
Device Number: 2
Vendor/Device ID Code x00011011
Vendor: x1011 Digital Equipment Corp.
Device: x0001 DECchip 21050 5.0V **PCI-to-PCI
Bridge**
Command Register x0146 I/O Space Accesses Response:
DISABLED
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x0280 Device is 33 Mhz Capable.
No Support for User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x02
Device Class Code x060400 Bridge Device: PCI to PCI Bridge
Sys Cache Line Size x10
Latency Timer Value xF8
Header Type x01 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00000000
Base Address Register 2 x00000000
Primary Bus Number x00 Primary Side Bus# is: 0
Secondary Bus Number x02 Secondary Side Bus# is: 2
Sub Bus Number x02
Secondary Lat Timer x00
IO Base x00
IO Limit x00
Secondary Bus Status x0280 Device is 33 Mhz Capable
No User Defineable Features
Capable of Fast Back-to-Back
DEVSEL# Timing <10:9>: Medium
Memory Base x0410
Memory Limit x0410
Prefetch Memory Base x4000
Prefetch Memory Limit x3FF0
Prefetch Mem Base -Upper x00000000
Prefetch Mem Limit-Upper x00000000
IO Base - Upper x0000
IO Limit - Upper x0000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x00
Interrupt Pin Being Used x00
Bridge Control x0003 Parity Error Response: Normal
Actions
Secondary SERR#, Asserts Primary
SERR#
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000F9C0400018
PCI: 0
Secondary Bus on Bridge: 2
Secondary Bus Device Number: 0
Vendor/Device ID Code x10201077
Vendor: x1077 QLogic
Device: x1020 QLogic ISP_1020A/1040A
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x0200 Device is 33 Mhz Capable.
No Support for User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Not Supported in Target
Device.
Device Select Timing: Medium.
Device Revision x02
Device Class Code x010000 Mass Storage: SCSI Bus Controller
Sys Cache Line Size x10
Latency Timer Value xF8
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00101001
Base Address Register 2 x04110000
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x04100000
Interrupt Line Routing x08
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000F9C0030018
PCI: 0
Bus: 0
Device Number: 3
Vendor/Device ID Code x00091011
Vendor: x1011 Digital Equipment Corp.
Device: x0009 DECchip 21140 10/100Mhz TULIP
Ethernet
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x0280 Device is 33 Mhz Capable.
No Support for User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x12
Device Class Code x020000 Network Controller: Ethernet
Controller
Sys Cache Line Size x00
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00100101
Base Address Register 2 x04011100
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x0C
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000F9C0040018
PCI: 0
Bus: 0
Device Number: 4
Vendor/Device ID Code x0001120F
Vendor: x120F Essential Communications
Device: x0001 Unrecognized Device Code
Command Register x0146 I/O Space Accesses Response:
DISABLED
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x0280 Device is 33 Mhz Capable.
No Support for User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x00
Device Class Code x020000 Network Controller: Ethernet
Controller
Sys Cache Line Size x00
Latency Timer Value xF8
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x04010000
Base Address Register 2 x00000000
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x10
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000F9C0050018
PCI: 0
Bus: 0
Device Number: 5
Vendor/Device ID Code x000F1011
Vendor: x1011 Digital Equipment Corp.
Device: x000F Device: DEFPA Description: FDDI
Interface
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x0280 Device is 33 Mhz Capable.
No Support for User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x01
Device Class Code x020200 Network Controller: FDDI
Controller
Sys Cache Line Size x00
Latency Timer Value xF8
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x04011000
Base Address Register 2 x00100001
Base Address Register 3 x04000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x14
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
--------------------- FRU Subpacket ----------------------
Length x004F
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 4. Slot Name: IOD0/1
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 0
Part Number B3040-AA
Serial Number AY64201650
Revision Level 32
Firmware RevLevel * NOT Logged *
Self Test Information * NOT Logged *
--------------------- FRU Subpacket ----------------------
Length x0053
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 10. B3050 Module (Left Hand)
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 0
Part Number B3050-AA
Serial Number AY65001435
Revision Level 32
Firmware RevLevel V3.0
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x0048
Class 1. System Resource Subpacket
Type 4. System Bus Bridge
Rev 2.
Bridge Level x0001 PRIMARY Sys Bus Bridge: system ->
bus_type
Bus Type x0002 System Bus to PCI Bus Bridge
Num Registers 10.
This Bus Bridge Phy Addr x000000FBE0000000
IOD# 1
Dev Type & Rev Register x06000032 CAP Chip Revision:
x00000002
B3040 Module Revision:
x00000003
B3050 Module Revision:
x00000000
B3050 Module Type: Left Hand
Internal CAP Chip Arbiter: Enabled
Device Class: Host Bus to PCI
Bridge
MC-PCI Command Register x42460FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol:
Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data
Transactions
Bridge ACCEPTS 64 Bit Data
Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use RD/MOD/WRT for <64 Byte Block
Mem Wrt
Wrt PEND_NUM Threshold: 6.
RD_TYPE Memory Prefetch Algorithm:
Short
RL_TYPE Mem Rd Line Prefetch Type:
Medium
RM_TYPE Mem Rd Multiple Cmd Type:
Long
ARB_MODE PCI Arbitration: Round
Robin
Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27>
x00000000
IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25>
x00000000
Interrupt Ctrl Register x00000003 Write Device Interrupt Info
Struct:Enabled
Intr Target Dev Register x0000003A Intr Trgt-0 Dev ID(Octal) o72
Intr Trgt-1 Dev ID(Octal) o0
Intr Target Addr Register x00006004 Int Trgt Data Struct Ofst
x00000001
Int Info Mem Trgt Pg Addr
x00000006
Int Trgt Adr Ext Register x00000000 Int Info Mem Upr Adr Bits
x00000000
Interrupt Mask0 Register x00000000
Interrupt Mask1 Register x00000000
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000FBC0010018
PCI: 1
Bus: 0
Device Number: 1
Vendor/Device ID Code x00011000
Vendor: x1000 NCR
Device: x0001 NCR 53C810 Fast/Narrow SCSI
Controller
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x0200 Device is 33 Mhz Capable.
No Support for User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Not Supported in Target
Device.
Device Select Timing: Medium.
Device Revision x02
Device Class Code x010000 Mass Storage: SCSI Bus Controller
Sys Cache Line Size x00
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x00
Base Address Register 1 x00104001
Base Address Register 2 x04444000
Base Address Register 3 x00000000
Base Address Register 4 x00000000
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x00000000
Interrupt Line Routing x04
Interrupt Pin Being Used x01
Min Bus Grant/Burst x00
Max Bus Latency x00
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000FBC0020018
PCI: 1
Bus: 0
Device Number: 2
Vendor/Device ID Code x00081011
Vendor: x1011 Digital Equipment Corp.
Device: x0008 DEC_KZPSA Fast-Wide-Differential
SCSI
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x02C0 Device is 33 Mhz Capable.
Device Supports User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x00
Device Class Code x010000 Mass Storage: SCSI Bus Controller
Sys Cache Line Size x10
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x80
Base Address Register 1 x04443004
Base Address Register 2 x00000000
Base Address Register 3 x00103001
Base Address Register 4 x04300004
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x04430000
Interrupt Line Routing x08
Interrupt Pin Being Used x01
Min Bus Grant/Burst x08
Max Bus Latency x7F
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000FBC0030018
PCI: 1
Bus: 0
Device Number: 3
Vendor/Device ID Code x00081011
Vendor: x1011 Digital Equipment Corp.
Device: x0008 DEC_KZPSA Fast-Wide-Differential
SCSI
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x02C0 Device is 33 Mhz Capable.
Device Supports User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x00
Device Class Code x010000 Mass Storage: SCSI Bus Controller
Sys Cache Line Size x10
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x80
Base Address Register 1 x04442004
Base Address Register 2 x00000000
Base Address Register 3 x00102001
Base Address Register 4 x04200004
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x04420000
Interrupt Line Routing x0C
Interrupt Pin Being Used x01
Min Bus Grant/Burst x08
Max Bus Latency x7F
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000FBC0040018
PCI: 1
Bus: 0
Device Number: 4
Vendor/Device ID Code x00081011
Vendor: x1011 Digital Equipment Corp.
Device: x0008 DEC_KZPSA Fast-Wide-Differential
SCSI
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x02C0 Device is 33 Mhz Capable.
Device Supports User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x00
Device Class Code x010000 Mass Storage: SCSI Bus Controller
Sys Cache Line Size x10
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x80
Base Address Register 1 x04441004
Base Address Register 2 x00000000
Base Address Register 3 x00101001
Base Address Register 4 x04100004
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x04410000
Interrupt Line Routing x10
Interrupt Pin Being Used x01
Min Bus Grant/Burst x08
Max Bus Latency x7F
================ System Resource Subpacket ===============
Length x0058
Class 1. System Resource Subpacket
Type 5. PCI
Rev 1.
PCI Device Registers ----
PCI Configuration Addr x000000FBC0050018
PCI: 1
Bus: 0
Device Number: 5
Vendor/Device ID Code x00081011
Vendor: x1011 Digital Equipment Corp.
Device: x0008 DEC_KZPSA Fast-Wide-Differential
SCSI
Command Register x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability;
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:
DISABLED
Parity Error Detection Response:
Normal
Wait Cycle Address/Data Stepping:
DISABLED
SERR# Sys Err Driver Capability:
Enabled
Fast Back-to-Back to Many Target:
DISABLED
Status Register x02C0 Device is 33 Mhz Capable.
Device Supports User Defineable
Features.
Fast Back-to-Back to Different
Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
Device Revision x00
Device Class Code x010000 Mass Storage: SCSI Bus Controller
Sys Cache Line Size x10
Latency Timer Value xFF
Header Type x00 Single Function Device
Built-in Self Test CSR x80
Base Address Register 1 x04440004
Base Address Register 2 x00000000
Base Address Register 3 x00100001
Base Address Register 4 x04000004
Base Address Register 5 x00000000
Base Address Register 6 x00000000
Expansion Rom Base Addr x04400000
Interrupt Line Routing x14
Interrupt Pin Being Used x01
Min Bus Grant/Burst x08
Max Bus Latency x7F
--------------------- FRU Subpacket ----------------------
Length x004F
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 5. Slot Name: IOD0/1
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 0
Part Number B3040-AA
Serial Number AY64201650
Revision Level 32
Firmware RevLevel * NOT Logged *
Self Test Information * NOT Logged *
--------------------- FRU Subpacket ----------------------
Length x0053
Class 2. FRU Subpacket
Type 1. Standard FRU
Rev 2.
Alphaserver 4x00 Specific
FRU Location 10. B3050 Module (Left Hand)
Self Test Status x00000002 Self-Test Status in Device
Specific FRU
Manufacturer Digital
Model 0
Part Number B3050-AA
Serial Number AY65001435
Revision Level 32
Firmware RevLevel V3.0
Self Test Information * NOT Logged *
================ System Resource Subpacket ===============
Length x0028
Class 1. System Resource Subpacket
Type 8. Power
Rev 2.
Number of Elements 2.
Element Type x0001 DC Power Supply
ID No 0.
Status x00000001 OK
Element Type x0001 DC Power Supply
ID No 2.
Status x00000001 OK
================ System Resource Subpacket ===============
Length x1EF4
Class 1. System Resource Subpacket
Type 10. System Initialization Log
Rev 1.
System Init Log
11:19.38 initializing overlays
11:19.38 XDELTA not enabled.
11:19.38 initializing flash index
11:19.38 hf_init
11:19.38 flash index count = 64, adr = cb50c
11:19.38 flash seq_minor = a0000, var_major = 560003
11:19.38 starting console on CPU 0
11:19.38 initializing file system
11:19.38 DDB Startup, phase = 0
11:19.38 initializing timer data structures
11:19.38 lowering IPL
11:19.38 CPU 0 speed is 3.35 ns (299MHz)
11:19.38 DDB Startup, phase = 1
11:19.38 access NVRAM
11:19.38 slot 7 - CPU
11:19.38 slot 6 - CPU
11:19.38 slot 5 IOD (6000) - hose 1
11:19.38 slot 4 IOD (6008) - hose 0
11:19.38 slot 3 - CPU
11:19.38 slot 2 - CPU
11:19.38 slot 1 - MEM
11:19.38 Loading startup overlays
11:19.39 DDB Startup, phase = 2
11:19.39 Loading start2 overlays
11:19.39 DDB Startup, phase = 3
11:19.39 expand memzone b 8000000 s 8000000
11:19.39 memzone: base = 1000000, mz_size = f000000
11:19.39 halt code = 34
11:19.39 PC = 17c
11:19.39 starting console on CPU 1
11:19.39 lowering IPL
11:19.39 halt code = 34
11:19.39 PC = 17c
11:19.39 starting console on CPU 2
11:19.39 lowering IPL
11:19.39 halt code = 34
11:19.39 PC = 17c
11:19.39 starting console on CPU 3
11:19.39 lowering IPL
11:19.40 CPU 1 speed is 3.35 ns (299MHz)
11:19.40 entering idle loop
11:19.40 CPU 2 speed is 3.35 ns (299MHz)
11:19.40 entering idle loop
11:19.40 CPU 3 speed is 3.35 ns (299MHz)
11:19.40 entering idle loop
11:19.47 entering idle loop
11:19.47 Executing iod_diag on device iod0
11:19.47 iod0 passed power-up tests
11:19.47 Executing iod_diag on device iod1
11:19.47 iod1 passed power-up tests
11:19.48 Executing pceb_diag
11:19.48 pceb passed power-up tests
11:19.48 Executing esc_diag
11:19.48 esc passed power-up tests
11:19.48 Executing ds1287_diag
11:19.48 toy passed power-up tests
11:19.48 Executing combo_diag
11:19.48 combo passed power-up tests
11:19.48 Executing ncr810_diag
11:19.48 n810 passed power-up tests
11:19.51 resetting the SCSI bus on pka0.7.0.1.1
11:19.51 port pka0.7.0.1.1 initialized, scripts are at 123140
11:19.52 KZPSA h/s/b/f/c/config_device/vec 1/2/0/0/1/11c200/b8
11:19.59 KZPSA h/s/b/f/c/config_device/vec 1/3/0/0/2/11c420/bc
11:20.05 KZPSA h/s/b/f/c/config_device/vec 1/4/0/0/3/11c640/c0
11:20.12 KZPSA h/s/b/f/c/config_device/vec 1/5/0/0/4/11c860/c4
11:20.19 resetting the SCSI bus on puf0.7.0.2000.0
11:20.19 clearing interrupt vector 00000098
11:20.19 free all semaphores
11:20.19 free all dynamic memory
11:20.22 DEFPA h/s/b/f/c/config_device/vect 0/5/0/0/0/11fdc0/a4
11:20.28 Created device: dkf0.0.0.2000.0
11:20.29 resetting the SCSI bus on puf0.7.0.2000.0
11:20.30 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:20.31 breaking virtual connection with sb 00121280
11:20.31 clearing interrupt vector 00000098
11:20.31 free all semaphores
11:20.31 free all dynamic memory
11:20.32 resetting the SCSI bus on puf0.7.0.2000.0
11:20.33 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:20.33 breaking virtual connection with sb 001215c0
11:20.33 clearing interrupt vector 00000098
11:20.33 free all semaphores
11:20.33 free all dynamic memory
11:20.34 resetting the SCSI bus on puf0.7.0.2000.0
11:20.35 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:20.45 breaking virtual connection with sb 001215c0
11:20.45 clearing interrupt vector 00000098
11:20.45 free all semaphores
11:20.45 free all dynamic memory
11:20.46 resetting the SCSI bus on puf0.7.0.2000.0
11:20.47 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:20.49 breaking virtual connection with sb 001215c0
11:20.49 clearing interrupt vector 00000098
11:20.49 free all semaphores
11:20.49 free all dynamic memory
11:23.52 expand memzone b 8000000 s 8000000
11:23.52 memzone: base = 1000000, mz_size = f000000
11:23.52 IP interrupt on CPU 0
11:23.52 IP interrupt on CPU 3
11:23.52 IP interrupt on CPU 2
11:23.52 resetting the SCSI bus on pka0.7.0.1.1
11:23.52 port pka0.7.0.1.1 initialized, scripts are at 10d420
11:23.55 SDTR with pka0.5.0.1.1 completed
11:23.57 KZPSA h/s/b/f/c/config_device/vec 1/2/0/0/1/11c200/b8
11:24.03 kzpsa0.7.0.2.1 dkb TPwr 1 Fast 1 Bus ID 7 P01
A10
11:24.08 KZPSA h/s/b/f/c/config_device/vec 1/3/0/0/2/11c420/bc
11:24.14 kzpsa1.7.0.3.1 dkc TPwr 1 Fast 1 Bus ID 7 P01
A10
11:24.19 KZPSA h/s/b/f/c/config_device/vec 1/4/0/0/3/11c640/c0
11:24.25 kzpsa2.7.0.4.1 dkd TPwr 1 Fast 1 Bus ID 7 P01
A10
11:24.30 KZPSA h/s/b/f/c/config_device/vec 1/5/0/0/4/11c860/c4
11:24.36 kzpsa3.7.0.5.1 dke TPwr 1 Fast 1 Bus ID 7 P01
A10
11:24.42 resetting the SCSI bus on puf0.7.0.2000.0
11:24.47 breaking virtual connection with sb 0010d560
11:24.47 breaking virtual connection with sb 00132220
11:24.47 breaking virtual connection with sb 00132e40
11:24.47 breaking virtual connection with sb 00132fa0
11:24.47 breaking virtual connection with sb 001332c0
11:24.47 breaking virtual connection with sb 00133420
11:24.47 breaking virtual connection with sb 00133580
11:24.47 clearing interrupt vector 00000098
11:24.47 free all semaphores
11:24.47 free all dynamic memory
11:24.50 DEFPA h/s/b/f/c/config_device/vect 0/5/0/0/0/11fdc0/a4
11:25.05 resetting the SCSI bus on puf0.7.0.2000.0
11:25.06 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:25.07 breaking virtual connection with sb 00132220
11:25.07 clearing interrupt vector 00000098
11:25.07 free all semaphores
11:25.07 free all dynamic memory
11:25.07 resetting the SCSI bus on pka0.7.0.1.1
11:25.07 port pka0.7.0.1.1 initialized, scripts are at 133ca0
11:25.08 KZPSA h/s/b/f/c/config_device/vec 1/2/0/0/1/11c200/b8
11:25.15 KZPSA h/s/b/f/c/config_device/vec 1/3/0/0/2/11c420/bc
11:25.22 KZPSA h/s/b/f/c/config_device/vec 1/4/0/0/3/11c640/c0
11:25.28 KZPSA h/s/b/f/c/config_device/vec 1/5/0/0/4/11c860/c4
11:25.35 resetting the SCSI bus on puf0.7.0.2000.0
11:25.35 clearing interrupt vector 00000098
11:25.35 free all semaphores
11:25.35 free all dynamic memory
11:25.38 DEFPA h/s/b/f/c/config_device/vect 0/5/0/0/0/11fdc0/a4
11:25.45 resetting the SCSI bus on puf0.7.0.2000.0
11:25.46 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:25.46 breaking virtual connection with sb 00133940
11:25.46 clearing interrupt vector 00000098
11:25.46 free all semaphores
11:25.46 free all dynamic memory
11:25.47 resetting the SCSI bus on puf0.7.0.2000.0
11:25.48 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:25.58 breaking virtual connection with sb 00133940
11:25.58 clearing interrupt vector 00000098
11:25.58 free all semaphores
11:25.58 free all dynamic memory
11:25.58 resetting the SCSI bus on puf0.7.0.2000.0
11:26.00 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
11:26.01 breaking virtual connection with sb 00133940
11:26.01 clearing interrupt vector 00000098
11:26.01 free all semaphores
11:26.01 free all dynamic memory
22:06.23 resetting the SCSI bus on puf0.7.0.2000.0
22:06.24 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
22:06.24 breaking virtual connection with sb 00133940
22:06.24 clearing interrupt vector 00000098
22:06.24 free all semaphores
22:06.24 free all dynamic memory
22:06.25 resetting the SCSI bus on puf0.7.0.2000.0
22:06.27 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
22:08.06 breaking virtual connection with sb 00133940
22:08.06 clearing interrupt vector 00000098
22:08.06 free all semaphores
22:08.06 free all dynamic memory
22:08.06 resetting the SCSI bus on puf0.7.0.2000.0
22:08.08 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
22:08.08 breaking virtual connection with sb 00133940
22:08.08 clearing interrupt vector 00000098
22:08.08 free all semaphores
22:08.08 free all dynamic memory
22:08.10 IP interrupt on CPU 3
22:08.10 IP interrupt on CPU 1
22:08.10 IP interrupt on CPU 2
22:08.10 resetting the SCSI bus on puf0.7.0.2000.0
22:08.12 sense key = 'Unit Attention' (29|00) from dkf0.0.0.2000.0
******************************** ENTRY 3
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 346.
Timestamp of occurrence 30-APR-1997 00:06:18
Host name shd50
System type register x00000016 AlphaServer 4000 Series
Number of CPUs (mpnum) x00000004
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
Software Flags x0000000300000000
IOD 0 Register Subpkt Pres
IOD 1 Register Subpkt Pres
Active CPUs x0000000F
Hardware Rev x00000000
System Serial Number AY65200676
Module Serial Number
Module Type x0000
System Revision x00000000
* MCHK 660 Regs *
Flags: x00000000
PCI Mask x0000
Machine Check Reason x0202 IOD-Detected Hard Error -OR-
DTag Parity Error (If Cached CPU)
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x00004B3600000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 x0000000000000007
PALTEMP1 xFFFFFC00005DC590
PALTEMP2 xFFFFFC000045F7D0
PALTEMP3 x0000000000004400
PALTEMP4 x00000000000F4017
PALTEMP5 x0000F980000003F8
PALTEMP6 x0000000000000000
PALTEMP7 xFFFFFC000045F210
PALTEMP8 x1F1E171515020100
PALTEMP9 xFFFFFC000045F540
PALTEMP10 xFFFFFC0000468F94
PALTEMP11 xFFFFFC000045F3A0
PALTEMP12 xFFFFFC000045F740
PALTEMP13 x0000000000006E80
PALTEMP14 x0000000000000000
PALTEMP15 x00000000000F0000
PALTEMP16 x0000020306600001
PALTEMP17 x0000000000000000
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFF90153740
PALTEMP20 x0000000000730000
PALTEMP21 xFFFFFC000045F770
PALTEMP22 xFFFFFC00005DDD90
PALTEMP23 x000000000FE2FA38
Exception Address Reg xFFFFFC0000468F94
Native-mode Instruction
Exception PC x3FFFFF000011A3E5
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode:
x0000000000000005
Interrupt Summary Reg x0000000000200000
External HW Interrupt at IPL21
AST Requests 3-0:
x0000000000000000
IBOX Ctrl and Status Reg x000000C160000000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will
Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts
Enabled.
ICACHE BIST (Self Test) Was
Successful.
TEST_STATUS_H Pin Asserted
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFFFF8000A0
Memory Mgmt Flt Sts Reg x0000000000014890
If Err, Reference Resulted in DTB
Miss
Fault Inst RA Field:
x0000000000000002
Fault Inst Opcode:
x0000000000000029
Scache Address Reg xFFFFFF000001904F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFFFFFFFFEFFF
Last Bcache Access Resulted in a
Miss.
Value of Parity Bit for Tag
Control Status
Bits Dirty, Shared & Valid is
Set.
Value of Tag Control Dirty Bit is
Set.
Value of Tag Control Shared Bit is
Set.
Value of Tag Control Valid Bit is
Set.
Value of Parity Bit Covering Tag
Store
Address Bits is Set.
Tag Address<38:20> Is:
x000000000007FFFF
Ext Interface Address Reg xFFFFFF000800060F
Fill Syndrome Reg x0000000000000C0C
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF00005E75BF
** IOD SUBPACKET -> ** IOD 0 Register Subpacket
WHOAMI x0000023A Module Revision 1.
CPU = 0
This Bus Bridge Phy Addr x000000F9E0000000
IOD# 0
Dev Type & Rev Register x06008032 CAP Chip Revision:
x00000002
B3040 Module Revision:
x00000003
B3050 Module Revision:
x00000000
B3050 Module Type: Left Hand
PCI-EISA Bus Bridge Present on PCI
Segment
Device Class: Host Bus to PCI
Bridge
MC-PCI Command Register x42460FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol:
Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data
Transactions
Bridge ACCEPTS 64 Bit Data
Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use RD/MOD/WRT for <64 Byte Block
Mem Wrt
Wrt PEND_NUM Threshold: 6.
RD_TYPE Memory Prefetch Algorithm:
Short
RL_TYPE Mem Rd Line Prefetch Type:
Medium
RM_TYPE Mem Rd Multiple Cmd Type:
Long
ARB_MODE PCI Arbitration: Round
Robin
Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27>
x00000000
IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25>
x00000000
Interrupt Ctrl Register x00000003 Write Device Interrupt Info
Struct:Enabled
Interrupt Request x00811010 Interrupts asserted x00011010
Hard Error
Interrupt Mask0 Register x00C51111
Interrupt Mask1 Register x00000000
MC Error Info Register 0 x00006E80
MC Bus Trans Addr<31:4>: 6E80
MC Error Info Register 1 x800E8A04 MC bus trans addr <39:32>
x00000004
MC Command is ReadMod0-Mem
CPU0 Master at Time of Error
Device ID: x00000002
MC error info valid
CAP Error Register x85000000 Error Detected but Not Logged
Non-existant memory
MC error info latched
PCI Bus Trans Error Adr x00000000
MDPA Status Register x00000000 MDPA Status Register Data Not
Valid
MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not
Valid
MDPB Status Register x00000000 MDPB Status Register Data Not
Valid
MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not
Valid
** IOD SUBPACKET -> ** IOD 1 Register Subpacket
WHOAMI x0000023A Module Revision 1.
CPU = 0
This Bus Bridge Phy Addr x000000FBE0000000
IOD# 1
Dev Type & Rev Register x06000032 CAP Chip Revision:
x00000002
B3040 Module Revision:
x00000003
B3050 Module Revision:
x00000000
B3050 Module Type: Left Hand
Internal CAP Chip Arbiter: Enabled
Device Class: Host Bus to PCI
Bridge
MC-PCI Command Register x42460FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol:
Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data
Transactions
Bridge ACCEPTS 64 Bit Data
Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use RD/MOD/WRT for <64 Byte Block
Mem Wrt
Wrt PEND_NUM Threshold: 6.
RD_TYPE Memory Prefetch Algorithm:
Short
RL_TYPE Mem Rd Line Prefetch Type:
Medium
RM_TYPE Mem Rd Multiple Cmd Type:
Long
ARB_MODE PCI Arbitration: Round
Robin
Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27>
x00000000
IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25>
x00000000
Interrupt Ctrl Register x00000003 Write Device Interrupt Info
Struct:Enabled
Interrupt Request x00800000 Interrupts asserted x00000000
Hard Error
Interrupt Mask0 Register x00C51111
Interrupt Mask1 Register x00000000
MC Error Info Register 0 x00006E80
MC Bus Trans Addr<31:4>: 6E80
MC Error Info Register 1 x800E8A04 MC bus trans addr <39:32>
x00000004
MC Command is ReadMod0-Mem
CPU0 Master at Time of Error
Device ID: x00000002
MC error info valid
CAP Error Register x85000000 Error Detected but Not Logged
Non-existant memory
MC error info latched
PCI Bus Trans Error Adr x00000000
MDPA Status Register x00000000 MDPA Status Register Data Not
Valid
MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not
Valid
MDPB Status Register x00000000 MDPB Status Register Data Not
Valid
MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not
Valid
PALcode Revision Palcode Rev: 1.21-3
******************************** ENTRY 4
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 345.
Timestamp of occurrence 30-APR-1997 00:06:18
Host name shd50
System type register x00000016 AlphaServer 4000 Series
Number of CPUs (mpnum) x00000004
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 302. ASCII Panic Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 1. Panic
ASCII Message panic (cpu 0): System
Uncorrectable
Machine Check
******************************** ENTRY 5
********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 344.
Timestamp of occurrence 30-APR-1997 00:06:15
Host name shd50
System type register x00000016 AlphaServer 4000 Series
Number of CPUs (mpnum) x00000004
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
Software Flags x0000000300000000
IOD 0 Register Subpkt Pres
IOD 1 Register Subpkt Pres
Active CPUs x0000000F
Hardware Rev x00000000
System Serial Number AY65200676
Module Serial Number
Module Type x0000
System Revision x00000000
* MCHK 660 Regs *
Flags: x00000000
PCI Mask x0000
Machine Check Reason x0202 IOD-Detected Hard Error -OR-
DTag Parity Error (If Cached CPU)
PAL SHADOW REG 0 x0000000000000000
PAL SHADOW REG 1 x0000000000000000
PAL SHADOW REG 2 x0000000000000000
PAL SHADOW REG 3 x0000000000000000
PAL SHADOW REG 4 x00004B3600000000
PAL SHADOW REG 5 x0000000000000000
PAL SHADOW REG 6 x0000000000000000
PAL SHADOW REG 7 x0000000000000000
PALTEMP0 x0000000000000000
PALTEMP1 x0000000000000000
PALTEMP2 xFFFFFC000045F7D0
PALTEMP3 x0000000000004400
PALTEMP4 x0000000000000000
PALTEMP5 x0000000000000000
PALTEMP6 x0000000000000001
PALTEMP7 xFFFFFC000045F210
PALTEMP8 x1F1E171515020100
PALTEMP9 xFFFFFC000045F540
PALTEMP10 xFFFFFC00002A4E7C
PALTEMP11 xFFFFFC000045F3A0
PALTEMP12 xFFFFFC000045F740
PALTEMP13 x0000000000006E80
PALTEMP14 x0000000000000000
PALTEMP15 x00000000000F0000
PALTEMP16 x0000020306600001
PALTEMP17 x0000000000000000
PALTEMP18 x0000000000000000
PALTEMP19 xFFFFFFFF901539D8
PALTEMP20 x0000000000730000
PALTEMP21 xFFFFFC000045F770
PALTEMP22 xFFFFFC00005DDD90
PALTEMP23 x000000000FE2FA38
Exception Address Reg xFFFFFC00002A4E7C
Native-mode Instruction
Exception PC x3FFFFF00000A939F
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
PAL Base Address Reg x0000000000014000
Base Addr for PALcode:
x0000000000000005
Interrupt Summary Reg x0000000000200000
External HW Interrupt at IPL21
AST Requests 3-0:
x0000000000000000
IBOX Ctrl and Status Reg x000000C160000000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.
Floating Point Instructions will
Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts
Enabled.
ICACHE BIST (Self Test) Was
Successful.
TEST_STATUS_H Pin Asserted
Icache Par Err Stat Reg x0000000000000000
Dcache Par Err Stat Reg x0000000000000000
Virtual Address Reg xFFFFFFFF90DB3F18
Memory Mgmt Flt Sts Reg x0000000000014150
If Err, Reference Resulted in DTB
Miss
Fault Inst RA Field:
x0000000000000005
Fault Inst Opcode:
x0000000000000028
Scache Address Reg xFFFFFF000001902F
Scache Status Reg x0000000000000000
Bcache Tag Address Reg xFFFFFFFFFFFFEFFF
Last Bcache Access Resulted in a
Miss.
Value of Parity Bit for Tag
Control Status
Bits Dirty, Shared & Valid is
Set.
Value of Tag Control Dirty Bit is
Set.
Value of Tag Control Shared Bit is
Set.
Value of Tag Control Valid Bit is
Set.
Value of Parity Bit Covering Tag
Store
Address Bits is Set.
Tag Address<38:20> Is:
x000000000007FFFF
Ext Interface Address Reg xFFFFFF000800060F
Fill Syndrome Reg x0000000000000C0C
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error Occurred During D-ref Fill
LD LOCK xFFFFFF00002008FF
** IOD SUBPACKET -> ** IOD 0 Register Subpacket
WHOAMI x0000023A Module Revision 1.
CPU = 0
This Bus Bridge Phy Addr x000000F9E0000000
IOD# 0
Dev Type & Rev Register x06008032 CAP Chip Revision:
x00000002
B3040 Module Revision:
x00000003
B3050 Module Revision:
x00000000
B3050 Module Type: Left Hand
PCI-EISA Bus Bridge Present on PCI
Segment
Device Class: Host Bus to PCI
Bridge
MC-PCI Command Register x42460FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol:
Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data
Transactions
Bridge ACCEPTS 64 Bit Data
Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use RD/MOD/WRT for <64 Byte Block
Mem Wrt
Wrt PEND_NUM Threshold: 6.
RD_TYPE Memory Prefetch Algorithm:
Short
RL_TYPE Mem Rd Line Prefetch Type:
Medium
RM_TYPE Mem Rd Multiple Cmd Type:
Long
ARB_MODE PCI Arbitration: Round
Robin
Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27>
x00000000
IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25>
x00000000
Interrupt Ctrl Register x00000003 Write Device Interrupt Info
Struct:Enabled
Interrupt Request x00800000 Interrupts asserted x00000000
Hard Error
Interrupt Mask0 Register x00C51111
Interrupt Mask1 Register x00000000
MC Error Info Register 0 x09190380
MC Bus Trans Addr<31:4>: 9190380
MC Error Info Register 1 x800FDA00 MC bus trans addr <39:32>
x00000000
MC Command is ReadMod0-Mem
CPU3 OR IOD3 Master at Time of
Error
Device ID: x00000007
MC error info valid
CAP Error Register xE0000000 Uncorrectable ECC err det by MDPA
Uncorrectable ECC err det by MDPB
MC error info latched
PCI Bus Trans Error Adr x00000000
MDPA Status Register x00000000 MDPA Status Register Data Not
Valid
MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not
Valid
MDPB Status Register x00000000 MDPB Status Register Data Not
Valid
MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not
Valid
** IOD SUBPACKET -> ** IOD 1 Register Subpacket
WHOAMI x0000023A Module Revision 1.
CPU = 0
This Bus Bridge Phy Addr x000000FBE0000000
IOD# 1
Dev Type & Rev Register x06000032 CAP Chip Revision:
x00000002
B3040 Module Revision:
x00000003
B3050 Module Revision:
x00000000
B3050 Module Type: Left Hand
Internal CAP Chip Arbiter: Enabled
Device Class: Host Bus to PCI
Bridge
MC-PCI Command Register x42460FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol:
Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data
Transactions
Bridge ACCEPTS 64 Bit Data
Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use RD/MOD/WRT for <64 Byte Block
Mem Wrt
Wrt PEND_NUM Threshold: 6.
RD_TYPE Memory Prefetch Algorithm:
Short
RL_TYPE Mem Rd Line Prefetch Type:
Medium
RM_TYPE Mem Rd Multiple Cmd Type:
Long
ARB_MODE PCI Arbitration: Round
Robin
Mem Host Address Ext Reg x00000000 HAE Sparse Mem Adr<31:27>
x00000000
IO Host Adr Ext Register x00000000 PCI Upper Adr Bits<31:25>
x00000000
Interrupt Ctrl Register x00000003 Write Device Interrupt Info
Struct:Enabled
Interrupt Request x00800000 Interrupts asserted x00000000
Hard Error
Interrupt Mask0 Register x00C51111
Interrupt Mask1 Register x00000000
MC Error Info Register 0 x09190380
MC Bus Trans Addr<31:4>: 9190380
MC Error Info Register 1 x800FDA00 MC bus trans addr <39:32>
x00000000
MC Command is ReadMod0-Mem
CPU3 OR IOD3 Master at Time of
Error
Device ID: x00000007
MC error info valid
CAP Error Register xE0000000 Uncorrectable ECC err det by MDPA
Uncorrectable ECC err det by MDPB
MC error info latched
PCI Bus Trans Error Adr x00000000
MDPA Status Register x00000000 MDPA Status Register Data Not
Valid
MDPA Error Syndrome Reg x00000000 MDPA Syndrome Register Data Not
Valid
MDPB Status Register x00000000 MDPB Status Register Data Not
Valid
MDPB Error Syndrome Reg x00000000 MDPB Syndrome Register Data Not
Valid
PALcode Revision Palcode Rev: 1.21-3
| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 582.1 | | MAY21::CUMMINS | | Wed Apr 30 1997 15:07 | 8 |
| See 578.10
This error footprint is one of diskless KZPSA (and it would seem to not
be from your replies to other notes) or SYNC memory on quad CPU with <
B07 system motherboard. The suggestion is that you try EDO memory, if
possible. Then, if the problem goes away, use the channels available to
get an updated motherboard. As with the other system, swapping CPUs is
not likely to solve the problem.
|
| 582.2 | | MAY21::CUMMINS | | Wed Apr 30 1997 15:09 | 9 |
| A question..
Are these failures (note 578 and this note) now being seen because you
have upgraded and added additional CPUs? I.e. what changed recently to
cause these errors to start to appear, if anything? Or are these newly
purchased machines?
Thanks,
BC
|
| 582.3 | Any machine check tool available for 4100 ? | LEMAN::MARTIN_A | Be vigilant... | Thu May 01 1997 04:08 | 8 |
| Are there any machine check tools available for troubleshooting
AS4100 machine checks ???
Looking forward to get one...
Cheers,
============================
Alain MARTIN/SSG Switzerland
|
| 582.4 | MCHECK tool 4100. | IJSAPL::RIETKERK | Bart Rietkerk-Hoogeveen-Holland | Thu May 01 1997 05:38 | 7 |
| Re .3
Alain,
See note 303.* in this conference....
Bart
|
| 582.5 | motherboard rev B07 solved my problem. | PANTER::AUBERT | | Fri May 09 1997 05:23 | 10 |
| I have changed the motherboard with revision B07. Since 2 days now the
system is working fine (no more machine check). I do not have checked
with EDO memory before but I will do it with another system which has
the same problem.
I would like to thank you for your advice since it solves my problem.
Regards,
Thierry Aubert/DEC at CERN
|