| Title: | AlphaServer 4100 |
| Moderator: | MOVMON::DAVIS S |
| Created: | Tue Apr 16 1996 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 648 |
| Total number of notes: | 3158 |
I read in the 4100 tech docs that the bus can get faster, with faster
CPs, a la 8400. Now, can anyone tell me what speed the bus runs at in
the 400, 466, and whatever the next one will be (mail offline, if we
can't discuss unnannouncos here). Also, the effect on B/W.
And, can someone help me understand: If we put bigger *and* faster
cache parts on the CP card, what effect does this have (in a generic
sense - I know it'd be caveated) on bus traffic. I infer, from what we
saw with 'improved' spec scaling for the 2100 with 8MB that *something*
must happen, but is it becuase the cache is bigger, or faster ?
(apologies if this sounds simple/daft - but I'm trying to learn whilst
selling... ;-)
ta,
AW
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 563.1 | Bus and cache speeds | POBOXB::STEINMAN | Mon Apr 07 1997 12:59 | 43 | |
For the 5/300 systems, the bus runs at 60MHz (16.67 nS)
For 5/400 and 5/466, the system bus runs at 66.6 MHz (15.0 nS)
Peak system bus bandwidth for 5/300 is 16 bytes per 16.67 nS = 960MB/s
5/4xx is 16 bytes per 15 nS = 1066MB/s
....can't discuss any future speeds here
In a generic sense, the larger the cache, the better the hit rate, so
the faster the perceived memory latency is. There are applications
that make very good use of increased cache size, while there are others
that will see no benefit.
Cache sizes for 4000/4100 are:
Model L1 L2 L3
===== == == ==
5/300e 8K 96K 0K
5/300 8K 96K 2048K
5/400 8K 96K 4096K
5/466 8K 96K 4096K
L1 latency is 2 cycles
L2 latency is 8 cycles, so these scale 100% with 21164 frequency
L3 latency is 19 cycles for 5/300, 21 cycles for 5/400, and 22 cycles
for 5/466 (63 nS, 52.5 nS, and 47 nS respectively), so these
latencies improve with 21164 frequency, but not 100%.
These latencies are for cache hits from when the LD instruction issues
to when the instruction that consumes the data issues. So the L3
latencies include all the on chip processing and the off-chip access
time to retrieve data from the module-level SRAMs. Roughly half the
latency is on-chip processing (11 cycles). The offchip component is:
5/300 8 cycles (26.67 nS, @ 16.67 nS rep-rate for successive
accesses)
5/400 10 cycles (25.00 nS, @ 15.00 nS rep-rate)
5/466 11 cycles (23.57 nS, @ 15.00 nS rep-rate)
/Mo
| |||||
| 563.2 | CPU clock = n*bus clock? | STAR::jacobi.zko.dec.com::jacobi | Paul A. Jacobi - OpenVMS Systems Group | Mon Apr 07 1997 14:10 | 11 |
Are CPUs clocked independantly of the bus speed, or is the CPU speed always a multiple of the bus speed? 5.0 * 60 = 300 6.0 * 66 = 396 (~400) 6.5 * 66 = 429 (~433) -Paul | |||||
| 563.3 | PCI speed? | NETRIX::"[email protected]" | Dave Cherkus | Mon Apr 07 1997 14:56 | 5 |
Does this mean the 300 MHz system runs its PCI bus at 30 MHz instead of 33 MHz? Or is the system bus speed and the PCI bus speed unrelated? Dave [Posted by WWW Notes gateway] | |||||
| 563.4 | clock divisor and speeds | POBOXB::STEINMAN | Mon Apr 07 1997 17:30 | 20 | |
Re .2:
The clock multiples are as follows:
Product CPU Frequency Divisor Bus Speed
====== ============= ======= =========
5/300e 300 MHz 5 60.00MHz
5/300 300 MHz 5 60.00MHz
5/400 400 MHz 6 66.67MHz
5/466 466.667 MHz 7 66.67MHz
Re .3:
The PCI bus is always run at 33MHz (It may actually be 33.33, I'll
check into that) regardless of CPU or system bus speed.
/mo
| |||||
| 563.5 | POBOXB::DUNCAN | Tue Apr 08 1997 11:25 | 3 | ||
PCI runs at 30nS - that is 33 1/3 MHz /SHD | |||||