| Title: | Embedded and Real Time Modular Computing Conference |
| Moderator: | IRNBRU::GRANT |
| Created: | Tue Sep 05 1995 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 235 |
| Total number of notes: | 1091 |
Multiple Processors in a PICMG environment:
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From: SHRCTR::SOMES 11-FEB-1997 15:35:17.89
To: CIMCAD::PIERSON
Subj: Multiple CPUs
Dave,
>Question: Is there a way (According to PCIMG spec) to elaborate more than one
>CPU board on the PCI Passive Backplane?
Answer(s):
1. Since the CPU slot is different mechanically from the other PCI slots on
the backplane, having the outline dimensions and ISA connector location of an
ISA card, it is mechanically impossible to plug more than one CPU in a
backplane (unless there are two CPU slots.)
2. In backplanes having two CPU compatible slots, the intent is to provide
additional mechanical clearance for CPUs with high heatsinks. The unused CPU
slot is usable only as an ISA slot. The CPU slot must also provide clock
distribution outputs, the REQx#/GNTx# pairs for each option slot with master
capability, and is the slot where the INTx lines are monitored. If two CPU's
were installed, these "system controller" functions would have to be disabled
on one of the two. Moreover, these extra signals make the PCI interface
electrically incmpatible with standard PCI option slots.
3. The PCI architecture makes multicomputing extremely difficult, since it
doesn't mandate configuration space registers on core logic PCI interfaces.
Thus if a PCI CPU were built to the mechanical specifications for PCI slot
cards, and were installed in a PCI option slot, it would not be enumerated by
the standard BIOS or firmware images we find on the current crop of system
controller platforms.
4. If a special BIOS or firmware image were implemented that permitted a PCI
CPU to be configured either as a system controller or an intelligent PCI
option, and allowed for manual allocation of the inbound address space
associated with the chip set, it might be possible to hack a multi-computing
environment.
5. As I understand it, the Intel i960RP has a PCI interface which responds to
configuration space accesses, making enumeration and address space assignment
by the system controller possible at powerup, and is therefore presumably
suitable for use as a compute element on the PCI bus. I've heard rumors that
future PCI core logic for StrongArm might do likewise.
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 185.1 | some ramblings | RTOEU::EGAUTHIER | AUA - Another Useful Abbreviation | Wed Mar 12 1997 08:38 | 54 |
"Multiprocessing on PICMG?"
Please clarify. Different people mean different things when they
multiprocessing.
For example, from the VME space, people usually mean multiple
processors in the same backplane running different operating systems,
but capable of shared memory.
Others, when they hear multiprocessing, think of servers with
multiple CPUs, single I/O and memory subsystems, and 1 operating
system running (SMP).
For the first example, I can envision new intelligent PCI cards which
may meet some peoples' definition of multiprocessing. These new
cards would use new bridging technology to allow for two seperate PCI
spaces within the same system (codename Drawbridge).
DISCLAIMER
----------
As far as I am aware, there is nothing like this under
development, or even planned. Here is an idea:
PICMG system. On the PCI, an I/O card that has a drawbridge
interface (giving it it's own local PCI bus, but allowing it to
appear as a device to the host system).
On the I/O card, behind the drawbridge, a foot-bridge (PCI
support bridge for StrongARM) and a StrongARM running your choice
of real-time OS. The card could then interface with the real
world in many different ways (PC104, Cardbus, Industry Pack, PMC,
your choice of field-bus, etc.)
Package a real-time OS with the board which is canned
(pre-configured to support a given application) and your
real-time OS is really just a device driver.
Now for the host system, we will probably need some software
support for mapping, and synchronization between the host
processor and the StrongARM.
What do you have? For the older folks out there, you will say
"VAX RTA". However you could have, a low end PLC (or a high end
PLC), or a powerful CNC machine, or a high end communications
box, or a high end data data acquisition system, or a real-time
video encoding box, or a ....well you get the idea...
Again, as far as I know, there are no plans in this area...but maybe
their should be.
Just thinking out loud.
-Eric
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| 185.2 | Multiprocessing .ne. SMP | BBPBV1::WALLACE | john wallace @ bbp. +44 860 675093 | Wed Mar 12 1997 09:08 | 21 |
Eric,
I know somebody (you knew him too) who apparently has done something
like you suggest in your "intelligent PCI cards" para (but with 21066
not StrongArm, and without Drawbridge).
As you say, it all depends on what the customer means by
multiprocessing.
With PCI, it's unlikely ever to be "one shared-memory OS across multiple
CPUs" ie what we commonly refer to as SMP. (Never? Maybe.) So what?
With the "attached processor(s)" concept there are lots of ways of
envisioning a system containing more than one processor, and
communicating in lots of interesting ways.
We definitely don't need to "just say no" when people ask about
multiprocessing.
regards
john
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