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| Title: | Embedded and Real Time Modular Computing Conference |
|
| Moderator: | IRNBRU::GRANT |
|
| Created: | Tue Sep 05 1995 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 235 |
| Total number of notes: | 1091 |
179.0. "EBM3x-PA: PCI Bus varia" by CIMCAD::PIERSON () Tue Mar 04 1997 16:35
More Q & A, answers from Eng'g....
>>1. Max burst transfer cycle on PCI bus/Rushmore
> There is no defined maximum burst tranfer specified by PCI.
> The number of burst cycles is controlled by the driver and Bios of
> the card in use.
> The Rushmore board itself can have a consecutive maximum
> burst count of 21 cycles for PCI reads and 22 burst cycles for PCI
> writes. The burst cycles gives a base PCI bandwidth of 112MB for
> read and writes, but the write performance is improved by a 512Byte
> write merging memory buffer to give a 121Mbytes write performance.
>>2. Is there any way to change the burst transfer cycle number?
> There is no way to control this inherently in the Rushmore
> BIOS. The BIOS or operating system driver can control this.
>>3. Default burst transfer cycle number
> BIOS and driver dependent. There may also be hardware
> limitation. The Bridge chips only have 32 Byte buffers that would
> have to stop on tranfers greater that 8 PCI Bursts. Other PCI
> devices may also have limitations that are beyond our control.
>Martin McGregor
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