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Conference nesbit::modular

Title:Embedded and Real Time Modular Computing Conference
Moderator:IRNBRU::GRANT
Created:Tue Sep 05 1995
Last Modified:Fri Jun 06 1997
Last Successful Update:Fri Jun 06 1997
Number of topics:235
Total number of notes:1091

177.0. "ECC test enable" by ATCJPN::ABE () Thu Feb 27 1997 04:35

Hi

I set the ECC test enable on BIOS/Rushmore, and save/exit from the BIOS.
After that, the system never come out.
I reseted BIOS, system come out.
What does this setting mean?

Thank you in advance

Kazushi
T.RTitleUserPersonal
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177.1CIMCAD::PIERSONThu Mar 06 1997 23:1412
    
    (and i quote:)
    
    	This will enable ECC test mode.  This ECC mode can detect and
    	correct single bit error[s], detect double bit errors, and detect all
    	errors confined to a single nibble.  When this mode is enabled, all
    	DRAM latencies are increased by one cycle.
    
    As a practical matter, it seems to be not working right...
    
    	regards
    	dwp
177.2Intended for Factory Use OnlyCIMCAD::PIERSONFri Mar 07 1997 19:5759
    After investigation by Engineering & Support team:
    
    
        _______________
        |d|i|g|i|t|a|l|
        |_|_|_|_|_|_|_| (tm)

        To: Eric Gauthier               Date: 7-Mar-1997
            Ron Sarkozy                 From: Dave Pierson
            Yasunori Kobayashi          Dept: TOEM Support Engineering
                                        Phone: 508-841-3020
                                        Loc/Mail Stop: SHR3-1/D20
                                        [email protected]

       Subject: EBM3x-PA (DMCC Pentium SBC)

       Please forward to the FAEs.

       Product:
              EBM3x-PA

       Short version:
              NO risk.

       Problem
       One of the settings in the BIOS set up function allows the user
       to make the SBC unusable.

       Fix:
       Leave the ECC Test Enable function as it is in the factory default.
       If it has been modified, reset it to the default, as below.

       ================================================================
       From the EBM3-PA vendor:

       >The "ECC Test" enable/disable setup question under the AMIBIOS Chipset
       >setup menu sets bit6 of TXC configuration register 50h3D 1.  This
       >forces DRAM memory parity data (MPD[7:0]) to "0" during DRAM writes. 
       >During reads, MPD[7:0] are compared according to the selected DRAM
       >integrity algorithm and the appropriate error status is generated.20

       >As you've probably realized, ECC test mode requires 36 bit SIMMs and
       >has little use outside of a manufacturing/engineering test environment:
       >when the ECC Test setup option is enabled, it essentially forces
       >errors to occur under normal circumstances.  This option may be removed
       >from from Setup in future BIOS releases.

       >If the user does enable ECC Test mode, the system may appear to hang.
       >If this happens, there are three methods of recourse:

       >       1) hold down the <INSERT> key during boot:
       >       this allows the user to enter Setup and change settings;

       >       2) hold down the <END> key during boot,
       >       this causes the BIOS to reload the Optimal Default settings; and

       >       3) remove the CMOS backup battery for 10 to 30 seconds, this
       >       clears the memory containing the BIOS settings.