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Conference nesbit::modular

Title:Embedded and Real Time Modular Computing Conference
Moderator:IRNBRU::GRANT
Created:Tue Sep 05 1995
Last Modified:Fri Jun 06 1997
Last Successful Update:Fri Jun 06 1997
Number of topics:235
Total number of notes:1091

99.0. "EBM3x-AA PCI 2.1 compliant ?" by PRSSOS::POTARD (Francois Potard - TOEM Design-Win - 858-1326) Wed Sep 11 1996 15:39

T.RTitleUserPersonal
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99.12.1 vs 2.0? what are differencesBBPBV1::WALLACEjohn wallace @ bbp. +44 860 675093Tue Apr 08 1997 16:4811
    See 134 for the V2.1 stuff (answer = "not yet").
    
    Actually, when I did some research on this for a customer a while ago,
    I thought I was given the answer "2.1 is the same functionally as 2.0
    but with minor editorial improvements in wording etc to resolve
    ambiguities and such". 
    
    I can't find where I put that info. Am I misremembering ?
    
    regards
    john
99.2CIMCAD::PIERSONTue Apr 08 1997 17:2316
    welllllllll.
    
    Coupla different things are getting blurred together, here.
    
    134.4(?) discusses _backplanes_.
    
    .0 inquires about SBC's, specifically, about the EBM3x-px, aka
    Rushmore.  As near as i can tell, Ebm3x-px IS PCI 2.1 compliant...
    
    There ARE technical Differences between PCI 2.0 and PCI 2.1, tho they
    are some where between oscure and abstruse.  (eg: I dunno).  However
    Digital Semiconductor saw fit to sell separate devices for each, so
    there IS a difference....
    
    	regards
    	dwp
99.3guess i wasn't paying enough attention...BBPBV1::WALLACEjohn wallace @ bbp. +44 860 675093Tue Apr 08 1997 18:052
    Ooops. Sorry (wish I could remember my sources for "2.0 = 2.1"; maybe
    Laurie Pegrum's chips seminar in Munich?).
99.4CIMCAD::PIERSONTue Apr 08 1997 20:4810
    Checked with the nearest wizard.  He sez:
    
>Dave,

>Most of the differences are editorial.  The only substantive changes I'm aware 
>of are the 66 MHz timing values and a rule that a Target must respond with 
>data in 16 clock ticks or terminate the transaction in RETRY.

    	regards
    	dwp
99.5PCI 2.1 protocol did change...POBOXA::DUNCANThu Apr 10 1997 20:1613
There are new ordering rules and a "delayed transaction" type that was
not specified in 2.0. The delayed transaction makes PCI a pended bus
and makes PCI to PCI bus bridges and peer-to-peer transactions
possible without deadlock.

For most applications the delayed transaction is transparent because
it looks like a retry.

There are changes to class-codes used by BIOS to associate devices to
drivers.

/SHD