Conference nesbit::modular

    The Interrupt Accelerator white paper is now in the IR.
    
    Thank you! 
    
    regards
    john

>                     -< Int Acc whitepaper arrived in IR >-

  Yeah, Donna S. had to deliver it there for the March update of the OEM
  InfoCenter -- along with another whitepaper (hard/soft), the Vx
  performance report, and new data sheets for DECtalk/DMCC/VxWorks.
  (The March update should go live in a week or so.)
  
  Fyi, all such items have to exist in the Web IR before a corporate web
  site can go live -- which is a good driver for getting them where they
  belong in the first place...
  
  (By contrast, a bunch of product doc is going on the OEM web site as well,
  but it doesn't need to go in the Web IR.)   - Jay

    The new DMCC flyer (LI01GF in VTX IR) has this to say about the
    interrupt accelerator (on p4, left of the OCP picture)
    
    "Interrupt accelerator technology: Found on all DIGITAL backplanes,
    this technology enables guaranteed PCI bus reads with two cycles when
    coupled with Alpha SBCs."

    urrrrrmmmm.
    
    It looks too loose to be true, but i could be missing summat without the
    rest of the context.
    
    What i would recognize as being 'true' would read more like:
    
    >    "Interrupt accelerator technology: Found on all DIGITAL backplanes,
    >   this technology enables guaranteed
    
    		IDENTIFICATION OF A PCI INTERUPT SOURCE WITHIN TWO
    		ISA bus 
    > bus reads
    
     >when coupled with Alpha SBCs."
      
    In other words, instead of having to 'poll' to determine the interupt
    source, the SBC does two reads (to ISA space) & gets a bit map of who
    is interupting.
    
    [The plain, ordinary, PCI bus ASSUMES a 'poll for interupts' model,
    as in a PC.  DMCC backplanes allow that, to go along with x86 based
    SBC's]
    
    regards
    	dwp

    I got a question from a customer (Lucent) asking about the physical
    implementation of the Interrupt Accelerator.  Ross Armstrong's white
    paper doesn't discuss that (see page 7, Column 2, "Physical
    Implementation" section):  "This paper is not intended to imply any
    particular physical implementation.  the generic functionality..."

    Is there anything I can share with this customer?  Another paper? 
    Perhaps a description here?  

    Thanks,
    Steve

    I recall seeing lot of information (an entire chapter devoted to
    PCI Interrupt Controller) in the Hardware Reference Manual for the
    Takara but that is still way off from being published.
    
    The HRM for K2 has gone to SSB.  My assumption is that the interrupt
    accelerator information therein should be identical.   
    
    We also licence the technology in case Lucent wants to implement
    it in in their backplanes.

    The implementation of most of the accelerator lives on the backplane.
    Its in an FPGA, or two...
    'other implemntations are possible' as the lawyers say...
    	regards
    	dwp

>    "Interrupt accelerator technology: Found on all DIGITAL backplanes,
>    this technology enables guaranteed PCI bus reads with two cycles when
>    coupled with Alpha SBCs."

   I think what they mean is; interrupting device can be determined
   within a guaranteed two [bus?] cycles.

   Ross, are you out there?

   In any case, what is written is incorrect.

   -Eric

>   I think what they mean is; interrupting device can be determined
>   within a guaranteed two [bus?] cycles.

Two ISA bus read cycles.


Gordon