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Conference wrksys::alphastation

Title:	Alpha Workstation Conference
Notice:	See note 1.* for conference notices
Moderator:	WRKSYS::HOUSE

Created:	Wed Sep 07 1994
Last Modified:	Fri Jun 06 1997
Last Successful Update:	Fri Jun 06 1997
Number of topics:	1996
Total number of notes:	9122

1891.0. "NON DEC MEMs on upgraded Alphastation 200 " by ATZIS2::DIETRICH_B () Fri Mar 14 1997 11:47

Hello,

I notify increasing memory problems on upgraded alphastations 200


History: 
--------
Customer bought Alphastations 200 4/100 and Alphastations 200 4/166
with memory of 32MB ( 2x 16 MB simms )

He upgraded memory with 1x 64MB ( 2x 32 MB simms ) oder 2x 64MB.
These mems are NON-DIGITAL.
The systems functioned O.K., and they were taken under contract 
inclusive NON-DIGITAL mems.

Last month the Alphastations 200 4/100 and Alphastations 200 4/166 
were upgraded to Alphastations200 4/233 using PB43U-AA and PB42U-AA
( cpu and quartz ).

Then the problems begun up to now with 1 or 2 calls concerning a crashing 
Alphastation per week.

Tests:
------
Problems happened on upgraded Alphastations 200 4/100 but it can be  
reproduced also on the former 4/166s ( using mems of 4/100 ).   
	
Customer operating-System is Digital-Unix 3.2, I tested mems on 
Alpha-Vms 7.1  with UETP ( and verfied bad mems )

Not all NON-DIGITAL mems are bad, a lot of them seem to be O.K. 
 
Question:
---------
- are there differences in memory management between
	Alphastation 200 4/100 or  4/166
   and  Alphastation 200 4/233 ?


Greetings, Bernd Dietrich, Austria

T.R	Title	User	Personal Name	Date	Lines
1891.1	details?	WRKSYS::SCHUMANN		`Fri Mar 14 1997 12:14`	11
	There should be no difference between basic memory timing on the various speeds of AlphaStation 200. Are you getting parity errors, or what is the nature of the crashes? If you psot the vendor part number from the chips on the SIMMs, I'll have a look to verify that these parts are "compatible". In general, "normal" ECC SIMMs should work in Mustang. If the DRAMs are marked -80 or -8, they are too slow. --RS
1891.2	more details	ATZIS2::DIETRICH_B		`Tue Mar 18 1997 07:11`	58
	Hello, there are the simm data 32 MB- Simms SIEMENS-Chips 16x HYB5117400BJ-60 ( 8 per side ) and 2x HYB514100BJ-60 ( 1 per side ) Mems were ordered from TRANSTEC partno.: MSP01/64 Crash was reproductible from UETP, LOAD suggesting 37, selected 65 users Bank 0: 2x 32MB , Bank 1: 2x 16MB Mem System crashed without dump, Halt Code 7 ---> Console >>> Errlog analysis with decevent: ------------------------------ Logging OS 1. OpenVMS System Architecture 2. Alpha OS version V7.1 Event sequence number 20. Timestamp of occurrence 14-MAR-1997 13:59:12 Time since reboot 0 Day(s) 2:26:39 Host name TIMAVB System Model AlphaStation 200 4/233 Entry type 23. Cache Error CPU Minor class 4. 620 System Correctable Error Byte Count x02E8 Processor Specific Offset x00000110 System Specific Offset x000001A0 PAL Error Type Code x00000092 D-Cache Parity Error PAL Frame Revision x00000001 Gretings Bernd Dietrich
1891.3	Dcache fill parity error	WRKSYS::HOUSE	Kenny House, Workstations Engineering	`Tue Mar 18 1997 08:33`	26
	This is really a Dcache fill parity error. Is there any chance of your getting the additional information below? -- Kenny House --------- 0x92 PRIMARY DCACHE DATA FILL PARITY ERROR BIU_STAT<11:10> = 01 Indicates that data with a parity error was received from Bcache or memory while performing a Dcache fill ANALYSIS: BIU_STAT<13:12> - Identifies the quadword within the hexaword primary cache fill block which caused the error. FILL_ADDR<33:5> - Contains the physical address associated with this error. FILL_SYNDROME - Indicates which longword within the identified quadword contained the error. BC_TAG<0> indicates whether the access hit in the Bcache.
1891.4	more info	ATZIS2::DIETRICH_B		`Thu Mar 20 1997 07:28`	313
	Hello, I repeated tests next day under nearly the same circumstances. The system never crashed again. ----- I installed 2 verified bad mems ( the day before ) to the same Simm locations and tested a long time. Those two mems will be tested by a SIMM-tester next week. Hope to get more info there. Here is the full entry, I could not locate BIU_STAT. Logging OS 1. OpenVMS System Architecture 2. Alpha OS version V7.1 Event sequence number 20. Timestamp of occurrence 14-MAR-1997 13:59:12 Time since reboot 0 Day(s) 2:26:39 Host name TIMAVB System Model AlphaStation 200 4/233 Entry type 23. Cache Error CPU Minor class 4. 620 System Correctable Error Byte Count x02E8 Processor Specific Offset x00000110 System Specific Offset x000001A0 PAL Error Type Code x00000092 D-Cache Parity Error PAL Frame Revision x00000001 - ALPHA CHIP REGISTERS - PALTEMP1 x000000000034E1D0 PALTEMP2 x0012C4F800000004 PALTEMP3 x0000000000000000 PALTEMP4 x00000000001E8E2B PALTEMP5 x0000000000000000 PALTEMP6 x000000000034E148 PALTEMP7 x0000000000004200 PALTEMP8 x0000000000000400 PALTEMP9 x000000000000001B PALTEMP10 x000000BCD121F39C PALTEMP11 x0000000000000000 PALTEMP12 x000000007AFFD500 PALTEMP13 x000000007AFFD81C PALTEMP14 x000000007AFFD564 PALTEMP15 x00000000001F0000 PALTEMP16 x00000000002032F8 PALTEMP17 x0000000000000001 PALTEMP18 x0000000000000003 PALTEMP19 x0000000000020044 PALTEMP20 xC044440100004100 PALTEMP21 x000000000034E144 PALTEMP22 x000000007FF92000 PALTEMP23 x0000000000000007 PALTEMP24 xFFFFFFFF8090A000 PALTEMP25 x0000000000090000 PALTEMP26 x000000007FFA2000 PALTEMP27 x0000000000000000 PALTEMP28 x0000000003060000 PALTEMP29 xFFFFFFFC00000000 PALTEMP30 x0000000000346000 PALTEMP31 x0000000006E7E080 Exception Address Reg x000000000020BA6A Exception Address Reg Provides Information About The Most Recent Exception. Address Points to Native-Mode Instruction If Machine Check or Math Trap Exception, PC in Exception Address is Correct. Last Exception Addr PC: x0000000000082E9A Exception Summary Reg x4672041345C01C8E Last Exception: Software Completion Invalid Operation Floating Inexact Error Exception Mask Reg IPR Window Bit Set Exception Mask Reg x441F0410C3FFFFF1 Exception Operation Result in Register I0 Exception Operation Result in Register I4 Exception Operation Result in Register I5 Exception Operation Result in Register I6 Exception Operation Result in Register I7 Exception Operation Result in Register I8 Exception Operation Result in Register I9 Exception Operation Result in Register I10 Exception Operation Result in Register I11 Exception Operation Result in Register I12 Exception Operation Result in Register I13 Exception Operation Result in Register I14 Exception Operation Result in Register I15 Exception Operation Result in Register I16 Exception Operation Result in Register I17 Exception Operation Result in Register I18 Exception Operation Result in Register I19 Exception Operation Result in Register I20 Exception Operation Result in Register I21 Exception Operation Result in Register I22 Exception Operation Result in Register I23 Exception Operation Result in Register I24 Exception Operation Result in Register I25 Exception Operation Result in Register I30 Exception Operation Result in Register I31 Exception Operation Result in Register F4 Exception Operation Result in Register F10 Exception Operation Result in Register F16 Exception Operation Result in Register F17 Exception Operation Result in Register F18 Exception Operation Result in Register F19 Exception Operation Result in Register F20 Exception Operation Result in Register F26 Exception Operation Result in Register F30 Icache Ctrl & Status Reg x0012C4F800000004 Performance Counters Disabled Empty Wrt Buffer Before Issuing Next Inst Branch Prediction Selection: Not Taken JSR Stack is Disabled Instructions Can Only Single Issue If Not in PALmode, Executing Reserved Inst Opcode Will Result in OPCDEC Exception. Super Page Istream Memory Mapping Disabled Float Point Inst Will Cause FEN Exception Icache Addr Space Numb: x0000000000000000 PALcode Base Address Reg x0000000000008000 PALcode Base Address: x0000000000000002 Hardware Int Enable Reg x00000001FFFFD4E0 CRD Error Interrupts Disabled CPU Hrdw Interrupts Enabled Irq_h Pins 0,2 CPU Hrdw Interrupts Enbld Irq_h Pins 3,4,5 Performance Cntr 0 & 1 Interrupts Disabled Serial Line Interrupts Disabled Software Interrupts Enbld on Level 1,2,3,4 Software Interrupts Enbld on Level 5,6,7,8 Software Interrupts Enbld Level 9,10,11,12 Software Interrupts Enbld Levels 13,14,15 AST Interrupts Enbld in Kernel, Executive, Supervisor, and User Mode. Hardware Int Request Reg x0000000000000000 NO Hrdw Int Req With Companion Enable Set NO Softw Int Req With Companion Enable Set NO AST Int Req With Companion Enable Set Memory Management CSR x00000000000017C0 MMCSR Valid Only on Mem Mgt Err, DTB Miss, D-Stream Fault, Dcache Parity Error. Last Faulting Instruction RA Field: R28 Last Faulting Instruction Opcode Follows: x0B - LDQ_U Load Unaligned Quadword (Data) Cache Status Reg x0000000000000023 This is EV45 Cache Status Register(C_STAT) EV45 Chip is Production Version of 21064A Last Load or Store Missed Dcache PARITY ERROR DETECTED in Icache Cache Address Reg x00000007FFFFFFFF Abox Control Reg x000000000000940A Machine Checks Enabled for Uncorr Errors CRD Interrupts Disabled Single Entry Icache Stream Buffer Enabled Lock Operation Conforms to Alpha Architect Dcache Enabled 16K Byte Dcache Selected Double Invalidate: Both EV45 Dcache Blocks Addressed By iAdr_h<12:5> Invalidated. Bus Interface Status Reg x0000000000002C40 PARITY ERROR In QW2 of Primary Cache Fill Block Hexaword During an Icache Fill. Bus Interface Address Reg x0000000007211A60 Address Only Valid if Bus Interface Status Register Error Bit 0,1,2, or 3 is Set. BIU Addr adr_h<33:5>: x00000000003908D3 Bus Interface Control Reg x0000000810002225 External Cache (Bcache) Enabled PARITY MODE: External Cache Parity Enabled Cache Rams are Output Enable Controlled Ext Cache Rd Access Time: 3 CPU Cycles Ext Cache Wrt Cycle Time: 3 CPU Cycles Size of External Cache: 256 Kbyte Ext Cache For Phys Addr Quad 3 Disabled Ext Cache Rd Time Controlling Bcache Reads Ext Cache Wrt En Ctrl: x0000000000000001 Fill Syndrome Reg x0000000000000001 IF ECC MODE (Bus Intf Ctl Reg Bit 1 Set), Low LW of Quadword Check Bit 00 Err. IF PARITY MODE(Bus Intf Ctl Reg Bit 1 Clr) Low LW of Quadword Corrupted. No Error in Upper Long Word of Quad Word Fill Address Reg x0000000007211A60 Addr Only Valid if Bus Interface Stat Reg ECC(Bit 8) or PARITY(Bit 10) Error Set. Cache Blk Phy Adr<33:5> x00000000003908D3 Virtual Address Reg x00000000000061D0 Dstream FLT/DTB Miss VA x00000000000061D0 Bcache Tag Reg x0000000000009494 Last Bcache Access Resulted in a Miss Parity Bit for Bcache Tag Status Bits Clr Bcache Tag Dirty Bit Set Bcache Tag Shared Bit Clear Bcache Tag Valid Bit Set Bcache Tag Addrress Parity Bit Clear Tag Being Probed: x00000000000004A4 coma_gcr x000000006D8D00A4 DMA Priority 64 bit wide MEM Bcache enabled Bcache long writes coma_edsr x0000000000002140 coma_ter x000000006D8DFFF8 sysTag<21:17> = x0000000000007FFC coma_elar x000000007D810000 sysBus<20:5> at time of e x0000000000000000 coma_ehar x000000007D810800 sysBus<33:21> at time of x0000000000000800 coma_ldlr x000000007D81C200 sysBus<20:5> last locked x000000000000C200 coma_ldhr x000000007D810041 sysBus<31:21> last locked x0000000000000041 coma_base0 x000000007D810000 Reg Base Adr <33:23> = x0000000000000000 coma_base1 x000000007D810100 Reg Base Adr <33:23> = x0000000000000080 coma_base2 x000000007D810200 Reg Base Adr <33:23> = x0000000000000100 coma_cnfg0 x000000007D810069 Bank Valid Bank Size = 64 MB Column Adr Selection x0000000000000001 coma_cnfg1 x000000006D8D0069 Bank Valid Bank Size = 64 MB Column Adr Selection x0000000000000001 coma_cnfg2 x000000006D8D004B Bank Valid Bank Size = 32 MB Column Adr Selection x0000000000000001 epic_dcsr xFFFFFFFF800C001D Translation buffer enabled Prefetch enabled Disable correctable error Pass 2 Chip Full Bypass PCI Cycle Type = IO Write epic_pear x0000000001220080 PCI error address x0000000001220080 epic_sear x000000000024E0D0 DMA Address = x0000000000024E0D epic_tbr1 x0000000000800000 Translation Base Adr = x0000000000004000 epic_tbr2 x0000000000000000 Translation Base Adr = x0000000000000000 epic_pbr1 x00000000000C0000 Scatter/Gather Enabled Window Enabled PCI Base Adr x0000000000000000 epic_pbr2 x0000000040080000 Scatter/Gather Disabled Window Enabled PCI Base Adr x0000000000000400 epic_pmr1 x000000001FF00000 PCI Mask x00000000000001FF epic_pmr2 x000000003FF00000 PCI Mask x00000000000003FF epic_harx1 xFFFFFFFF80000000 PCI_ad - memory space = x0000000000000010 epic_harx2 x0000000000000000 PCI_ad - memory space = x0000000000000000 epic_pmlt x00000000000000FF Master Latency Timer = 255. epic_tag0 x0000000001011000 Entry Valid pci_page x0000000000000202 epic_tag1 x0000000001219000 Entry Valid pci_page x0000000000000242 epic_tag2 x000000000100B000 Entry Valid pci_page x0000000000000201 epic_tag3 x0000000001221000 Entry Valid pci_page x0000000000000244 epic_tag4 x0000000001230000 pci_page x0000000000000246 epic_tag5 x000000000100A000 pci_page x0000000000000201 epic_tag6 x0000000001218000 pci_page x0000000000000242 epic_tag7 x0000000001001000 Entry Valid pci_page x0000000000000200 epic_data0 x0000000000000938 cpu_page x000000000000024E epic_data1 x0000000000000A48 cpu_page x0000000000000292 epic_data2 x0000000000000344 cpu_page x00000000000000D1 epic_data3 x0000000000000910 cpu_page x0000000000000244 epic_data4 x00000000000003F0 cpu_page x00000000000000FC epic_data5 x0000000000000344 cpu_page x00000000000000D1 epic_data6 x0000000000000A4A cpu_page x0000000000000292 epic_data7 x000000000000094E cpu_page x0000000000000253 Greetings Bernd Dietrich