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Conference rusure::math

Title:Mathematics at DEC
Moderator:RUSURE::EDP
Created:Mon Feb 03 1986
Last Modified:Fri Jun 06 1997
Last Successful Update:Fri Jun 06 1997
Number of topics:2083
Total number of notes:14613

1620.0. "Formal verification of Alpha" by RICKS::LEONARD (Tim Leonard, Cantab) Tue Jun 02 1992 15:53

    I've got a job opening that might be of interest to this community.
    
    I'm looking for a senior or principal engineer to help me do formal
    verification of Alpha processors.  I need someone with experience
    in formal verification, and familiarity with computer architecture.
    The group is in Hudson, Massachusetts, and can provide relocation and
    a flexible starting date: any time in Q1.  I need to make a decision
    this month (June).  If you're interested, contact me at Ricks::Leonard,
    or DTN 225-6451. 

    We are part of the Semiconductor Engineering Group, and are responsible
    for verifying the functional correctness of chip designs, particularly
    CPU designs.  We are trying to bring in formal methods and put them
    into use.  We expect to complete a formal specification of the Alpha
    architecture (already underway), formally verify PALcode, formally
    verify parts of Alpha processor designs, and build tools for making
    verification more efficient.  We expect to work in collaboration with
    research groups at Digital and at universities.  Though some of the
    work is research, all of it will be verifying real designs --- we're
    not doing academic work.
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