Conference ricks::dechips

    
    How about a prestoserve board?  It has the DMA engine and local
    storage which would be required for the task that you describe.
    Hope you're interested in unix or else it's start from scratch
    on the drivers.  N/S in the chart means Not Supported and the
    chart is from the Alphaserver 4100 supported options list.
    
    Dennis
    
    
    Part No.     Description                     VMS     UNIX     NT    Max
    
    DJ-ML200-AA  2MB PCI Prestoserve NVRAM       N/S     4.0B     N/S   1
    DJ-ML200-BA  4MB PCI Prestoserve NVRAM       N/S     4.0B     N/S   1
    DJ-ML200-CA  8MB PCI Prestoserve NVRAM       N/S     4.0B     N/S   1
       

re .1, .0

I don't think this will be easy, since you need to DMA twice, once
from memory to the Prestoserve board (that's easy) and once from
the Prestoserve board to the Memory Channel adapter. The latter may not
be supported by the existing driver. Also, the data will be on the PCI
twice, so it's hard to imagine that this will accelerate the process
vs. what you could achieve with programmed I/O from a CPU.

--RS

    Yes we are interested in UNIX.  We thought about Prestoserve but
    we concluded that the double copy was too wasteful.
    
    -Ed
    

    Re .1, DECwest Engineering does have a number of efforts and
    experimentations with PrestoServe in the Windows NT space.  These are
    both for our TL works as well as other platforms.
    
    --svb

Interesting thread.

I hadn't thought of Presto in this context.  My initial thoughts were to 
use Pamette (http://www.research.digital.com:80/SRC/pamette/) to avoid 
the problem mentioned above: under UNIX, Presto is not a shared resource,
it is solely managed by the file system and the driver, and it would be
tough to break this relationship.  Pamette is available and even operates
in 64 bit wide PCI mode (but your 8400 system does not, sigh). The negative 
is that you would have to do a bunch of Pamette firmware (Xilinx, anyone?) 
as well as UNIX infrastructure.

But the killer is the extra copy (mitigated somewhat by 64 bit where available
and by Pamette's near-thoretical-max performance). As I understand PCI you
just can't get what you want directly i.e. you can't get one device to
move data for a second device without an extra copy across the bus.  You
would have to do a fairly concise analysis of the microarchitecture to 
see if freeing up the CPU and system bus bandwith would cover the cost of 
the extra copy. 

Of course it would be ideal if the MC board had a DMA engine on-board.
It would free up a lot of CPU cycles currently used to move data around
as well as a lot of system bus bandwidth spent moving data into the
CPU that the CPU never needs to look at.  It would also allow the MC
board to be more in control of its destiny performance-wise, instead
of relying on the stream of Alpha instructions that get coded to move 
the data.  It would increase its throughput with TCP/IP, because the
TCP/IP base code pretty much presumes there is a DMA engine moving data 
out to the cable while the CPU is building the next packet.  It would
scale well because each active MC board would have its own DMA engine
instead of sharing a backplane resource.  I have made these points
in the past but they have not been embraced.

In summary, I can't see a simple way to get what you want.  All of
the ideas above have significant costs associated with them.  This
may or may not change in the future based on things like i2o (see
previous refs to i2o in this conference).  Or. hopefully, someone
else has better ideas.

Dave
[Posted by WWW Notes gateway]

Put the MC on a secondary PCI (behind a PPB) and
use Footbridge/StrongARM to move the data.

/SHD
=======================================================================
From:	PONYEX::PONYEX::MRGATE::"SALES::A1::SEMICONDUCTOR"  3-MAR-1997 11:03:08.08
To:	@Distribution_List
CC:	
Subj:	CORE LOGIC CHIP OPTIMIZES StrongARM MICROPROCESSOR                     1

From:	NAME: Semiconductor Sales & Mkting   <SEMICONDUCTOR@A1@SALES@PKO>
To:     See Below

From  Marianne Fisher, HLO

                NEW CORE LOGIC CHIP OPTIMIZES StrongARM
              MICROPROCESSOR FOR PCI EMBEDDED APPLICATIONS

...Enables Low-Cost/High-Performance Clients, Controllers, PC Add-Ins...

MAYNARD, Mass., March 3, 1997 -- Digital Equipment Corporation today
announced a single-chip core logic device that enables the StrongARM
SA-110 microprocessor to control popular, high-performance peripheral
devices on the PCI (Peripheral Component Interconnect) bus.  The 21285
core logic chip optimizes the StrongARM SA-110 microprocessor for a wide
variety of PCI embedded applications such as internetworking, office
automation, storage control, telecommunications, PC add-in devices, and
network clients.

Also announced was a toolset to enable developers to build and test
StrongARM PCI designs.

"The PCI bus provides the high bandwidth -- up to 132 megabytes per
second -- that manufacturers need to deliver high-performance products
for data-intensive applications," said Matt Theall, PCI bridge product
marketing manager for Digital Semiconductor, a Digital Equipment
Corporation business.  "Our StrongARM SA-110 and 21285 chips allow
designers to take advantage of PCI speeds for demanding applications
including network routers and switches, PBX equipment, cellular base
stations, storage drive and RAID controllers, intelligent I/O cards."

Integrates Advanced Features

The 21285 integrates advanced features to maximize StrongARM PCI
performance.  They include a synchronous DRAM interface for high data
rates, flash ROM interface for device initialization, DMA and interrupt
controllers, programmable timers, intelligent I/O (I2O) message unit,
parallel and serial ports, and a PCI bus arbiter.  The 21285 chip also
supplies the four clocks and chip selects for the SDRAMs.

With its superior power efficiency, low cost, and highest performance
among embedded processors, the StrongARM SA-110 is well suited to
embedded PCI applications as:
*    a network computer;
*    a local processor on an add-in card to provide intelligent I/O
     control, such as for a RAID controller;
*    an attached processor or accelerator on the host PCI bus.

In each case, the 21285 core logic chip provides the memory and bus
control, timing, PCI bus arbitration, and I2O message functions as
needed.

Tornado Support Announced

Wind River Systems, Inc., announced that it will offer its Tornado
application development system for the StrongARM SA-110 microprocessor.
A beta version of the Tornado system to support the SA-110 and the 21285
core logic chip will be available in the second quarter of 1997, with
formal release to follow in the fourth quarter.

"The Tornado system provides embedded designers using the StrongARM
processor the best development environment for bringing products to
market on time and within budget," said Dave Larrimore, vice president
of marketing at Wind River Systems.  "We are pleased to support the
StrongARM and 21285 chips as one of the highest performance solutions
for PCI embedded applications."

Pricing, Availability

The 21285 core logic chip for the StrongARM SA-110 is priced at $19.50
in quantities of 10,000.  Samples will be available in the second
quarter of 1997.

Design Toolset Offered

Digital Semiconductor will offer a complete toolset for StrongARM PCI
designs, comprising an evaluation module, containing the StrongARM
SA-110 and 21285 core logic chips, and the StrongARM Software Developers
Kit.  The kit includes a compiler, assembler, linker, debugger, and a
functional simulator model.  The design database for the evaluation
module, including schematics and related documentation, will also be
available.

The mature development environment and the number of third-party
realtime operating systems available for StrongARM microprocessors will
enable embedded designers to build and test hardware and software
subsystems, run benchmarks, and port applications.

Digital Semiconductor, a Digital Equipment Corporation business
headquartered in Hudson, Massachusetts, designs, manufactures and
markets industry-leading semiconductor products including Alpha
microprocessors and PCI chips for networking, bridging, and multimedia,
plus low-power StrongARM microprocessors under license from Advanced
RISC Machines Ltd.  Mitsubishi Electric Corporation and Samsung
Electronics Company Ltd. are alternate sources for Alpha
microprocessors.  Web site:  http://www.digital.com/semiconductor

Digital Equipment Corporation is a world leader in open client/server
solutions from personal computing to integrated worldwide information
systems.  DIGITAL's scalable Alpha and Intel platforms, storage,
networking, software and services, together with industry-focused
solutions from business partners, help organizations compete and win in
today's global marketplace.

                                 #####

Note to editors:

DIGITAL, Digital Semiconductor, and the DIGITAL logo are trademarks of
Digital Equipment Corporation.  StrongARM is a trademark of Advanced
RISC Machines Ltd.  Tornado is a trademark of Wind River Systems, Inc.
Intel is a registered trademark of Intel Corporation.


      
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To Distribution List:

If the data passes twice on the embedded PCI, the max throughput per
option is still only half a PCI bus.

If you're doing a card design, just use an adapter (PLX9060 or AMCC xxx)
that has a built-in DMA engine.

--RS

    And lest somebody suggest an Intel 960 based solution (960 processor
    and memory controller and PPB in one chip), the internal architecture
    of today's 960 chips has an equivalent bottleneck as the secondary PCI
    would have in the StrongArm based solution.
    
    At least using a secondary PCI would mean that the system PCI would be
    less busy.  The fact that the secondary PCI is saturated would not
    matter except so far as it limits ultimate performance.
    
    Steveg

A question with respect to the last two replies: can these approaches
(strongarm+footbridge or alternate PCI interface chip) be implemented
without remanufacturing the existing MC board i.e. through some sort of
daughterboard or mezzanine scheme?  Or are they presuming the ability
to remanufacture the MC board?  We are all talking in the realm of
the hypothetical.  I'm just wondering how far we are going.

-- 
Dave Cherkus                 UniMaster, Inc.       [email protected]
On contract to Digital                             [email protected]
[posted by Notes-News gateway]

re .9

To add these components you would need to redesign the module, and it's not an easy
change either.

If you are trying to reduce CPU utilization (which I assumed
was the goal) then it makes sense to use an embedded IOP
such as StrongARM. If efficient use of the PCI is your goal
then .7 is correct - these solutions don't buy anything.

For the purpose of an experiment you could probably use a
Footbridge evaluation board and MC card without change. To
deploy a product the MC card needs to be redesigned.
                     
Peer-to-Peer transactions targeting MC reduce CPU
utilization by as much as 70% on the AlphaServer 4100 - and
may be significant enough to look at using an IOP on an 8400
to the same end.

/SHD

    
    The footbridge eval. boards won't be available until Oct.
    
    -Ed