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Conference ricks::dechips

Title:Hudson VLSI
Notice:For Digital Chip Data - CHIPBZ::PRODUCTION$:[DS_INFO...]
Moderator:RICKS::PHIPPS
Created:Wed Feb 12 1986
Last Modified:Fri Jun 06 1997
Last Successful Update:Fri Jun 06 1997
Number of topics:701
Total number of notes:4658

663.0. "question on 'out-of-order' execution" by SNOFS1::JONESCHRIS (Chris Jones) Mon Mar 24 1997 23:09

Sorry for the repeat on this, but I can't find what I am looking for.

There was some work done on basic theoretical gain that a processor achieved by 
using 'out-of-order' execution over standard in-line processing.  By memory, the 
gain was around 10-15% (silicon for silicon, clock for clock).

Can anyone confirm/deny or provide pointer

many thanks
T.RTitleUserPersonal
Name
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663.1DenialKAMPUS::NEIDECKEREUROMEDIA: Distributed Multimedia ArchivesTue Mar 25 1997 03:1212
    There is no such rule (it somehow would imply that you needed to
    change a little bit in control logic in a design and keep everything
    else constant). To the best of my knowledge, nobody has done it
    that way ever.
    
    The primary advantage of OOO execution is that it can dynamically
    discover parallelism and dynamically disambiguate memory references.
    On certain floating point codes that makes over 100% difference.
    
    Other than that, look up die sizes, clock speeds and SPEC ratings
    for various processors and try to make up this nonexistent rule of
    thumb.
663.2+40% has been given hereNETRIX::"[email protected]"Bjorn FehrmWed Mar 26 1997 00:1810
Hello,

a Hudson  guy who used to work at HPs chip activity proposed out of order as a
speedup for Ev5+. He wrote HP had reach the conclusion it gave approx 40%
extra on a typical design everything else constant.

Can't remeber the number of the note.

Bj�rn
[Posted by WWW Notes gateway]
663.3GEMEVN::GLOSSOPOnly the paranoid surviveWed Mar 26 1997 10:3515
Any "number" is dependent on a variety of factors, including:

    - Estimates of memory latency (e.g. the longer memory latency is measured
      in "issue slots", the more likely reordering will have an impact)

    - Various factors in a particular processor implementation (including
      if it is a "short tick" style design, etc.)

    - The instruction set

    - The properties of the code being executed (i.e. was it already scheduled
      based on some latency being present, etc.)

My personal guess is that ev6 will benefit considerably more than many
of the competitors given all of these.