Conference ricks::dechips

Hmmm, title should say 120 Mio. Transistors

	Within 18 months? From HP? Yea, right.. Maybe in my 
	lifetime, but within 18 months? They don't exactly have
	a track record for accomplishing these goals.

	If we announced what we will have in 18 months, jaws would
	drop. At least DS has a reputation of meeting announcement
	goals.

	Ask HP about the much vaunted HP/Intel (or is that Intel/HP)
	chipset. Any solid dates on that? With solid performance
	numbers? Yup, didn't think so.


							mike

> in systems within 18 months

I'd like to see a chart for the "popular" CPUs/systems listing announcement 
date, announced availability date, actual availability date, and maybe announced 
performance, actual performance.

Anybody tracked this kind of thing over the last few years? It might make an 
excellent marketing tool.

PJDM

    >  If we announced what we will have in 18 months, jaws would drop.
    
    I am just dying for a Digital marketing person to explain to me why the
    hell we don't do this.  Yes, maybe HP won't ship it in 18 months.  Who
    cares??  They get the spotlight today, and that means they'll be around
    to deliver it someday, even if its 3 years down the road.  Few will
    remember that they slipped, and fewer still will care.  We can be
    conservative, and say how great we are at delivering what we promise,
    but it won't matter if we haven't put our cards on the table!!  Can't
    we hire a marketing exec that is willing to put out a press release
    *immediately* in response to HP, hyping up EV6, 64-bits, etc.?  I know
    I'm preaching to the choir -- I'll shut up now.
    
    	Steve

    You can get a copy of the COMPCON paper at
    
    www.hp.com/computing/framed/technology/micropro/pa-8500/docs/8500.html

    amazing...
    
    HP's much vaunted P7 gambit goes extremely pear-shaped, such that huge
    chunks of what they have been 'promising' their punters look like lies,
    yet their Marketing machine seems to be able to cover up the mess by
    making very loud noises about their new servers ('up to 5 times faster
    than...'), announcing the PA-8200, pre-pre announcing the PA-8500, and
    giving us another kick with a revised K460 TPC number...
    
    I'll leave it to Shak and Henning to ponder on how many TPM-C this
    vapourious piece of silicon can help deliver. But, the I-stream
    bandwidth should be good (John, isn't this what helps HP with the
    existing K460 numbers ?). This attribute is emphasised in the
    announcement paper.
    
    Also, *if* this ever happens, it does effectively de-couple HP from
    relying on ever faster cache chips, plus associated periphery, from
    external suppliers.
    
    The paper (ref as -1) states that this is still development. Anyone in
    semi want to *speculate* as to what an EV7 in CMOS 8 would look like.
    Write the goddam paper - talk about 'design goals' and 'objectives',
    discuss various 'options' etc. Don't mention any dates or specifics
    though. Just like HP's paper. I think this is called 'Marketing'.
    
    
    

    DIGITAL doesn't do marketing.
    
    But if anybody wanted to take what was announced each year at e.g.
    Microprocessor Forum (or whatever it's called) where we described the
    21264 recently, and all the other pre-announcements, and consolidate a
    "predicted" vs "reality" (on both dates and performance) we'd have an
    interesting tool.
    
    Anybody got the conference proceedings for the last few years ?
    
    regards
    john

HP> Since there are 1.5MB of instruction and data cache on the PA-8500,
HP> covering three-quarters of the die, ...

Can anyone estimate the size of this die, and the resulting manufacturing
cost?

EV6 has less than 1/10 as much cache, occupying perhaps 40% of its 3 cm� die
(based on Jim Keller's Microprocessor forum presentation in 
	http://www.digital.com/semiconductor/a264up1/index.html ).

So, EV6 uses about 0.4*3.0 = 1.2 cm� for its cache.  HP stores 1500/128 times
as much data, but in a process that's 2x as dense -- if it uses a similar RAM
cell, its cache would occupy 1500/128 * 1.2/2 = 7 cm�.  If that's 3/4 of the
chip, then the whole PA-8500 chip should be 9.4 cm�, or nearly 1.5 square
inches.

This doesn't sound manufacturable to me.  But based on the size of the non-RAM
parts of the chip, the above calculation makes the chip seem too big by about a
factor of 2.5   Perhaps HP is using a different approach to the RAM design. 
Since they use a banked cache, it only needs to cycle at the CPU clock rate
(not given in the paper, but perhaps 400 MHz?), while EV6's cycles at 2x the
CPU clock rate -- in the 0.25� technology that might mean cycling 4x as fast as
HP's design.  Could HP use a dynamic RAM cell for this cache, like we did for
CVAX (I think)?

Based on the size of the non-RAM parts of the chip, the above calculation
makes the chip seem too big by about a factor of 2.5

    A quick check of past press releases, references and HP product
    announcements... with respect to predictability
    
    PA8000
    
    12/20/93	Infoworld	PA8000 family products in 96-97 timeframe
    
    6/13/94	Dataquest Analysis	products available late 96
    
    3/95	COMPCON		Official chip announcement, product early
    				96
    11/2/95	HP Press rel.	samples available, product rollout early 96
    
    3/96	CEBIT		PA8000 based systems shown uder NDA
    
    5/96	PH Press rel	Servers available in Sept
    
    5/28/96	HP 		PA8000 K-series workstations
    
    9/13/96	HP		K-series servers introduced.
    
    Since the K-series WS and server are the same hardware, obviously,
    there were other issues for the delay.  (marketing, software ??)
    
    PA8200
    
    3/4/95	HP press rel	Schedule to follow the PA8000 by 12-18
    				months
    3/24/95	PC Week		PA8200 based systems   "mid to late 97"
    
    .
    .
    .
    3/19/97	if reports are correct 	 Systems announcement
    
    Best, the PA-8500 projected schedule be taken seriously, as well as 
    performance estimates.
    
    Barry  
    
    
    

    Q1CY95 - (March)	HP announces PA-8000 chip        
    			- systems early 1996
    Q4CY95 - (November)	HP announces PA-8000 chip *again*
    			- systems Q1CY96
    Q1CY96 - (April)    HP announces PA-8000 chips *again*
    			- systems "next month"
    Q2CY96 - (June)	HP announces PA-8000 workstations
    			- available "next month"
    Q3CY96 - (Aug/Sep)	PA-8000 systems finally ship
    
    								-mr. bill

    yeah, but i doubt the people buying them now give a rip ...

.6> I'll leave it to Shak and Henning to ponder on how many TPM-C this
.6> vapourious piece of silicon can help deliver. But, the I-stream
.6> bandwidth should be good (John, isn't this what helps HP with the
.6> existing K460 numbers ?). This attribute is emphasised in the
.6> announcement paper.
    
    This was originally Dick Sites' analysis, and I don't think it has been 
    disproved by anyone.
    
    HP has been getting a lot of mileage out of their cache approaches.  We
    should think very carefully about their alleged plans.

    so, as a 'cheap' fix for us, we could do a fast EV5 in Samsung's
    'CMOS-7' sort of process, but look to keep the die size large, and
    stuff a big piece of I-cache on board [as opposed to making the die
    small, aka PC type alpha]. And crank the damn thing as fast as
    possible.
    
    Yes, I *know* that I will criticised for being such a heretic, ("thou
    shalt not mumble anything likely to delay EV6 / Wildfire (insert
    favourite late project here..)). But I know EV5/6 works (today), and I
    am sure that *if* we chose, we could do this quite quickly.
    
    Right now, in the field, we are getting killed, by SUN and HP. And the
    latest HP noise just sounds to me like someone hitting a nail into a
    coffin. Yes, I *know* that sales and marketing etc need fixing too, but
    our core proposition needs to stack up. I can sell this junk, but the
    junk is getting harder and harder to sell.
    
    Oh, and it's not just the raw performance of a uni-CPU. Sun UE4000 and
    HP K460 and IBm J40 etc have a *packaging* advantage over us, in that
    with a single system they seem to be able to straddle several of ours.
    Why oh why can I only sell a 16 slot '4100' if it has 2 CPUs ? Huh ?
    
    Yeah, OK, a bit of a rant, and its late on a Sunday. Wales got beat by
    England at rugby and I am not happy. But doing my day job just seems to
    get harder and harder.                                             
    
    Anyone in GMA listening ? We may not make it to EV6 and Wildfire....
    
    
    AW

    Can you be more specific. What do you (and others) believe would
    comprise a set or family of machines that could would be
    "competition killers". Be specific, as to # cpu's, memory expansion,
    # PCI slots, expandability and cost. What features are "must have"
    features. 
    
    
    						/Dave
    

    Mr. Williams is a rare breed: a successful, articulate AlphaServer
    salesperson in the company who tries to engage engineering via NOTES. 
    We should nurture him and encourage his feedback (as Dave did in .14).
    
    I also think he's right...we should take HP cache designs more
    seriously than we appear to.
    

>     HP CONTINUES LEADERSHIP WITH NEW, HIGHEST-PERFORMANCE PA-RISC 
>     MICROPROCESSOR 
>     
>     Most Powerful PA-RISC Chip Breaks the 1MB On-chip Memory Barrier;
>     Dramatically Reduces Microprocessor Complexity and
>     Overall Computer-system Costs
>     
>     
>     
>     SAN FRANCISCO, March 12, 1997 -- Aggressively advancing its
>     leadership in commercial and technical computing and providing 
>     customers with a clear roadmap into the future, Hewlett-Packard 
>     Company today announced the PA-8500, the company's most powerful 
>     microprocessor to date and the industry's first chip to break the 1 
>     megabyte (MB) on-chip memory barrier.
>     
>     
>     Initial details of the newest member of the PA-8000 family of 
>     64-bit PA-RISC(1) microprocessors were announced here at the Uniforum 
>     trade show.
>     
>     The company's memory breakthrough -- incorporating 1.5MB cache 
>     memory on the chip -- gives the PA-8500 five times more on-chip memory 
>     than any other microprocessor.  The unrivaled cache, enabled by the 
>     company's adoption of an advanced .25-micron chip-making process, is 
>     expected to deliver breakthrough performance in technical and 
>     commercial environments.  These applications include Internet access, 
>     database access and management, computer-aided design and 
>     manufacturing (CAD/CAM), communications and transaction processing.
>     
>     
>     In fact, the numerous advancements incorporated in the PA-8500 
>     enable it to nearly triple the performance of the company's 
>     record-setting PA-8000, which is at the heart of currently shipping HP 
>     servers and systems.  Additionally, for many applications, such as 
>     financial transactions, online airline reservations and routine 
>     telephone connections, HP believes the PA-8500 will process 
>     information up to five times faster than competitive microprocessors 
>     currently on the market.
>     
>     
>     Performance Breakthrough
>     
>     HP's adoption of the 0.25-micron process is what gave the 
>     company the increased room on the chip; literally every functional 
>     component on the device was shrunk into considerably smaller space.  
>     HP took the opportunity afforded by this newfound room to incorporate 
>     the large on-chip cache memory.  The increased space also allowed for 
>     a dramatic increase in the amount of intelligence that could be 
>     integrated onto the device, greatly improving branch-prediction 
>     accuracy.
>     
>     
>     The 1.5MB of on-chip cache allows the CPU to operate more 
>     efficiently while executing instructions.  This is particularly 
>     advantageous in large commercial applications, such as transaction 
>     processing, which routinely require critical applications to be 
>     performed simultaneously.  Additionally, because systems built around 
>     the PA-8500 no longer require
>     expensive cache memory and require fewer parts, the chip cache reduces 
>     the overall cost of systems built around the PA-8500.
>     
>     "The demands of our customers are not standing still, and neither 
>     are we," said Richard W. (Rich) Sevcik, HP vice president and general 
>     manager of the Systems Technology Group.  "They're telling us they 
>     want their computers and applications to help them be more 
>     competitive, today and into the next decade.  We've designed a chip 
>     that -- within 18 months -- will drive new computers that will set new 
>     applications performance standards. 
>     By moving with us through the PA-8000 evolution and our transition to 
>     Merced, customers are assured of the industry's strongest road into 
>     the future.  And nothing could provide more opportunities for 
>     competitive advantage."
>     
>     
>     Innovative Design
>     
>     Like the PA-8000 and the PA-8200, the PA-8500 is a scaleable 64-bit 
>     microprocessor with multiprocessing capabilities, branch prediction 
>     and four-way out-of-order execution features, all of which enable 
>     industry-leading application performance.  The new chip is the 
>     company's first to use a .25-micron process and more than 120 million 
>     transistors.  
>     
>     
>     By further exploiting the powerful PA-8000 architecture, HP is 
>     ensuring that advancements in the PA-8500 also support applications 
>     from the PA-8200 and PA-8000.  This assures software developers and 
>     customers that the investments they have made in applications that run 
>     on HP's earlier PA-RISC processors will continue to pay off in the 
>     future.
>     
>     
>     PA-RISC Background
>     
>     From its inception in 1986, PA-RISC technology was designed to 
>     extend well into the next century.  HP designed PA-RISC in a 
>     simplified, modular fashion to accommodate future technologies, 
>     decrease system-design costs and reduce time to market for new 
>     products.  HP offers the industry's broadest line of RISC-based 
>     workstations and business systems and servers and last week was named 
>     the leading vendor -- for the seventh consecutive year -- in the 
>     commercial RISC/UNIX(R) system market by market-research firm Aberdeen 
>     Group of Boston.  Aberdeen's research showcased HP as owning 52 
>     percent of the commercial RISC/UNIX system market. 
>     
>     
>     Demand for RISC-based computers has grown steadily since 
>     the first commercially available RISC systems were shipped in the 
>     mid-1980s.  Currently, PA-RISC technology spans HP systems, ranging 
>     from low-end workstations to large-scale, 14-way symmetric 
>     multiprocessing systems with mainframe-class performance to enterprise 
>     parallel servers, scaleable to 224 processors.  This demonstrates 
>     PA-RISC's inherent scaleability, a
>     primary objective of its original definition, and protects customers' 
>     hardware and software investments in this architecture.  
>     
>     
>     Hewlett-Packard Company is the leading global manufacturer 
>     of computing, communications and measurement products and services 
>     recognized for excellence in quality and support.  HP has 112,800 
>     employees and had revenue of $38.4 billion in its 1996 fiscal year.
>     
>     
>     Information about HP and its products can be found on the 
>     World Wide Web at http://www.hp.com.
>     
>     
>     # # #
>     
>     
>     (1) PA-RISC stands for Precision Architecture-reduced-instruction-set 
>     computing.
>     
>     UNIX is a registered trademark in the United States and other 
>     countries, licensed exclusively through X/Open(R) Company Limited.
>     
>     X/Open is a registered trademark, and the X device is a trademark of 
>     X/Open Company Ltd. in the UK and other countries.
>     

    
    * Late Monday, senior executives of HEWLETT PACKARD CO outlined
      the roadmap for HP's future computing systems, saying customers
      can expect up to 15 times greater performance over the next
      five years. The executives, briefing reporters at company
      headquarters, said Hewlett-Packard plans to ease customers into
      new technologies that will support both its own blend of the
      Unix operating system and MICROSOFT CORP's Windows NT. The
      company said it plans to introduce fast new systems with
      greater multiprocessing capabilities as early as May. (Reuters
      08:23 PM ET 04/07/97) For the full text story, see
      http://www.merc.com/stories/cgi/story.cgi?id=2314425-40a