Conference ricks::dechips

Title             3D Graphics: A Technology Comes of Age                      
Instructor        Lynn Thorsen-Jensen           
Date              10-FEB-97 - 10-FEB-97
Time              1:30 -  3:30
Location          Cafe Annex HLO2-2/N4          
		  ARGO to Austin
		  Videotapes will be available in HLO, Palo Alto and
			Austin libraries.
Course Number     73C03-HA

Registration	  No Registration required                                    
                  
ABSTRACT          Three-dimensional graphics make use of the
                  widest bandwidth available between humans and computing
                  systems: our eyes.
                                                                                
                  With the advent of consumer-level awareness of 3D graphics,
                  the emphasis on the technology at the low-end has brought
                  out a wide array of vendors, movers-and-shakers, and
                  markets that threaten to topple the king-of-the graphics
                  hill, Silicon Graphics. What does this mean to the
                  technical market? Are there still opportunities for the
                  traditional graphics vendors? What does Digital stand to
                  gain or lose from the momentum building in this area?
                                                                                
                  This two-hour presentation starts with 3D computer graphics
                  fundamentals, gives an overview of the development of the 3D
                  technology and markets, and ends with a discussion of
                  DIGITAL as a supplier of this technology.
                                                                                
                                                                                
                                                                                
ABOUT THE SPEAKER:  Lynn Thorsen-Jensen is the Graphics Line                    
                  Manager for Graphics & Multimedia in the Workstation
                  Business Segment.  She joined Digital in April of 1996,
                  bringing with her 14 years of 3D graphics expertise from
                  her years with Evans & Sutherland.  Evans & Sutherland is
                  a high-performance computer graphics company based in
                  Salt Lake City, Utah.  Her last position at E&S was
                  Director of Marketing, where she managed the marketing
                  resources, product management, PR, and marketing
                  communications for a line of high-performance 3D
                  graphics accelerators. She is well-known in the field
                  of computer graphics and has served on many industry-wide
                  panels.
 
    

TITLE:   COMPCON '97  Presentations
SPEAKERS:  Ray Hookway, Peter Bannon, Dan Leibholz
DATE:  February 18th
TIME:  2:00pm - 3:30pm
ROOM:  Cafe' Annex, HLO2


Overview:

  Compcon is one of the country's preeminent computer technology conferences.
  Sponsored by the IEEE's Computer Society it has been held annually since 1955.
  This years compcon will be held from February 23rd through the 26th in San 
  Jose' California.  DIGITAL is proud to have three papers being presented at
  this year's conference by Engineers from Digital Semiconductor. The papers
  complete a session entitled "DEC Alphas: Servers to Desktop". Individually
  they are:
  
           1.  Digital FX!32: Running x86 Applications on Alpha NT
           2.  The Alpha 21164PC Microprocessor 
           3.  The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor

  The seminar being held in Hudson on the 18th will feature these three
  papers.  It is a chance for those Digital employees not able to attend
  compcon to hear the presentations as well as to give our speakers practice
  in front of a friendly audience.   The abstracts, in the order that they
  will be presented in Hudson, follow.   For more information on compcon
  check out:  http://www.compcon.org/


Title: Digital FX!32: Running x86 Applications on Alpha NT
Speaker: Ray Hookway
Abstract: 
DIGITAL FX!32 is a unique combination of emulation and binary
translation which makes it so that any 32-bit program which runs on an
x86 system running Windows NT 4.0 will install and run on an Alpha
Windows NT 4.0 system. After translation, x86 applications run as fast
under DIGITAL FX!32 on a 500Mz Alpha system as on a 200Mz Pentium-Pro.

The emulator and its associated runtime provide for transparent
execution of x86 applications. The emulator uses translation results
when they are available and produces profile data which is used by the
translator. The translator provides native Alpha code for the portions
of an x86 application which have been previously executed. A server
manages the translation process for the user, making the overall
process completely transparent.



Title:  The Alpha 21164PC Microprocessor 
Speaker:  Peter Bannon
Abstract:
The internal architecture of a 2000 MIPS/1000 MFLOPS (peak)
high-performance low cost  CMOS Alpha micro-processor chip is 
described.  This implementation is derived from the Alpha 21164
microprocessor to reduce cost while maintaining high performance.
It contains a quad-issue super-scalar instruction unit, two
64-bit integer execution pipelines, and two 64-bit floating
point execution pipelines.  The memory unit and bus interface
unit have been re-designed to provide a high performance memory
system using industry standard PC SRAM and DRAM components.



Title: The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor
Speaker:  Daniel Leibholz
Abstract:

The 21264 is a 500 MHz, Out-Of-Order, quad-fetch, six-way issue 
microprocessor. The aggressive cycle-time of the 21264 in combination 
with many architectural innovations, such as out-of-order and speculative 
execution, enable this microprocessor to deliver an estimated 30 SpecInt95 
and 50 SpecFp95 performance. In addition, the 21264 can sustain  5+ 
Gigabytes/sec of bandwidth to an L2 cache and 3+ Gigabytes/sec to 
memory for high performance on memory-intensive applications.

    

 
 
--------------------------------------------------------------------------------
                  EDE Custom Courses Description
________________________________________________________________________________
Title             CMOS Device Course for DIGITAL Semiconductor                
Instructor        Demitri Antoniadis            
Date              17-MAR-97 - 04-APR-97
Time              2:00 -  5:00
Location          Mt. Washington Conf HLO2-1/M10
Course Number     73CDC-HA
Registration      Log into COURSES software on SHARE  
                  Username is COURSES and password is EDUCATION.
Cancellation      Please cancel prior to course start date                    
                                                                              

Note              Course dates will be:
                  3/17, 3/19, 3/24, 3/25, 3/31, 4/2, 4/7,
                  and 4/9.
                                                                                
                  Time will be 2-5 pm.
                                                                                
Title:            CMOS Device Course for DIGITAL Semiconductor
                                                                                
Prerequisites     Some familiarity with basic semiconductor device physics.
                  E.g. course participants must have heard about electrons
                  and holes, about diodes and transistors and have seen
                  their simpified physical structure.  It is not be assumed
                  that they understand device operation.
                                                                                
Audience          Circuit designers that wish to know more about MOSFETs
                  the evolution of CMOS generations and what
                  is behind  SPICE models such as MOS10 and 11, tech-
                  files and limitations.
                                                                                
Description       The aim of this course is to provide a comprehensive
                  discussion on MOSFET operation and modeling so that
                  the compact models used in Spice and the technology
                  parameters and their variation can be appreciated.
                  Technology and physical constraints on MOSFET scaling and
                  associated MOSFET performance will be discussed.
                  Participants will experience hands-on the scaling constraints
                  through a comprehensive device design problem.
                  Model limitations and their range of validity will
                  be presented.  Parasitic elements and their relation
                  to technology will be discussed.  The charge control
                  point of view will be maintained throughout.
                                                                                
Outline           Semiconductors, Contacts, and the PN Junction.
                     - Quick review of doping, depletion, junction capacitance,
                       internal electrostatic potential, and current flow
                       in semiconductors.
                                                                                
                  The Two-Terminal MOS Structure.
                     - Surface change components, accumulation, depletion,
                       inversion.  Weak and strong inversion.  C-Vs.
                                                                                
                  The Three-Terminal MOS Structure.
                     - Independent contact to the invesion layer.  Substrate
                       bias effect.
                                                                                
                  The MOS Transistor, long-channel view.
                     - Qualitative model development.  Weak, moderate, and
                       strong inversion.  Vth, and Vth control by I/I.
                                                                                
                  MOS Transistors with Short and/or Narrow Channels.
                     - Charge sharing effect and its impact on Vth and
                       Idoff vs Leff and Vdd.  Effect of velocity saturation
                       on Idsat vs Leff.  The concept of device dimensions
                       and Vdd scaling with technology generations.

                                                                                
                  elected scaling-related topics.
                     - Vdd scaling and its effect on performance. tox scaling
                       effects on performance, Idoff and physical constraints.
                       Impact of poly OCV scaling.  Cov scaling trends and
                       impact on circuits.  Latchup.
                                                                                
                  "Unconventional" scaling issues.
                     - Energy minimization considerations. Very low voltage
                       operation concerns: OCV, temperature, subthreshold
                       behavior, Vth matching.  SOI CMOS: Differences from bulk
                       and its impact at CMOS6 and beyond.
                                                                                
                  MOSFET dynamic operation - charge-control view.
                     - The MOSFET as a dissipative switch.
                       Intrinsic and parasitic charges and capacitances.
                       Quasi-static and non-quasi-static operation.

    

    
    EDE    Employee Development and Education
    
    TSS    Technical Seminar Series 
    
    Title:  Morph: An Environment for Platform-specific Optimization
    Speaker:  J. Bradley Chen, Harvard University
    Date:  Feb. 25th
    Time:  10:00am - 12:00pm
    Location:  Mt. Washington

Abstract:

Modern high-performance microprocessors with their deep pipelines,
multi-level memory systems, and superscalar microarchitectures
provide ample opportunities for profile-driven, machine-specific
optimizations.  Unfortunately, these opportunities often go
unexploited because of the complexity of applying profile-driven,
machine-specific optimizations.  Morph is a unique compilation
and executable-rewriting environment that makes the aggressive
optimization of applications based on machine-specific
characteristics and user profile information practical. In this
talk I will describe our current Morph prototype for Digital UNIX.
Our results to date show that profile information can be collected
with negligible run-time overhead and that the resulting profiles
are of a sufficient quality to drive a code-layout optimization.

    

 
 
   EDE - Employee Development and Education 
 
--------------------------------------------------------------------------------
                  EDE Technical Seminar Series Description            
________________________________________________________________________________
Title             Developing Optimization in Machine SUIF: A Work-in-progress 
Speaker           Michael D. Smith,  Harvard University              
Date              27-FEB-97 - 27-FEB-97
Time              10:00 - 12:00
Location          Cafe Annex HLO2-2/N4          
Course Number     73TSS-08
Registration      Not required.                              

Title:            Developing Optimizations in Machine SUIF:
                  A Work-in-progress Talk
                        
                                                                                
Abstract:                                                                       
                                                                                
                  Modern high-performance microprocessors with their
                  deep pipelines, multi-level memory systems, and
                  superscalar microarchitectures provide ample
                  opportunities for profile-driven, machine-specific
                  optimizations.  In this talk, I describe our
                  Machine-SUIF extension of the Stanford SUIF compiler
                  system, which supports the development of these kinds
                  of optimizations.  We are designing our compiler so
                  that we do not have to re-develop the code for individual
                  optimizations when we change platform targets.  I introduce
                  Machine SUIF through the discussion of three on-going
                  research projects: a transformation for near-optimal
                  intra-procedural branch alignment; a code-placement
                  algorithm using temporal-ordering information; and a
                  library for building global instruction schedulers.
                  I present preliminary results for these optimizations
                  when targeting Digital Alpha microarchitectures.
                                                       
                   SUIF = Stanford University Intermediate Format,
                  For More Info. check out:  http://suif.stanford.edu/    
 
--------------------------------------------------------------------------------
Engineering Training and Education
Supporting Digital Semiconductor

    

   +---------------------------+ TM
   |   |   |   |   |   |   |   |
   | d | i | g | i | t | a | l |	      INTEROFFICE MEMORANDUM
   |   |   |   |   |   |   |   |
   +---------------------------+ 
   
   TO:  HLO SITE DISTRIBUTION			     
 	                                      FROM:  Peter J. Starvaski
                                              DEPT:  Human Resources
                                              EXT:   225-4701
                                              LOC:   HLO2-2/K12
                                              ENET:  SHARE::STARVASKI
						   
   SUBJECT:  COURSE ANNOUNCEMENT:

              "BASICS OF SUPPLY CHAIN MANAGEMENT"

    APICS, an internationally renown organization specializing in the
    mechanics of Supply Chain Management will be conducting a three day
    course for Digital Semiconductor Employees on March 19th, 20th, and 21st.

    This was designed as a closed course, however a limited number of seats
    have become available.  This course is not in our on-line database.
    If you'd like to participate please send mail to SHARE::STARVASKI. 

    The program provides an overall understanding of the entire flow of
    the supply chain,  from forecasting techniques through distribution.

    The eight modules that compose the program are detailed below.


OUTLINE:

Session 1--Introduction to Materials Management
  This session has two primary goals. The first is to help the participant
  understand the role of manufacturing in our economy and the basic types
  of manufacturing processes. The second is to describe materials management
  and to discuss the need for materials management.

Session 2--Forecasting
  In this session, the participant will learn the factors influencing demand.
  The participant will also learn basic principles of forecasting and learn the
  sources of forecast error. In addition, participants will acquire an under-
  standing of the principles of data collection.

Session 3--Master Planning
  This session gives participants fundamental information about the purpose 
  and function of production planning and master production scheduling. Topics
  covered in this session include manufacturing planning and control, making a
  production plan, developing a make-to-stock production plan, resource 
  requirements planning, and developing a master production schedule.

Session 4-Material Requirements Planning
  In this session, participants will learn the nature of demand and the use of
  material requirements planning. They will learn the purposes and formats of
  bills of material. Lead time and its components are also discussed in this
  session.

Session 5-Capacity Management and Production Activity Control
  This session has two purposes. The first is to provide a basic understanding
  of capacity management, and the second is to provide a basic understanding
  of the function and operation of production activity control. Participants 
  will learn how to determine rated or calculated capacity and will learn to
  describe the basic techniques of scheduling.

Session 6--Inventory Fundamentals
  In this session, methods of inventory management will be described, and 
  participants will learn the necessity for good inventory management and the 
  costs of ordering and carrying inventory. In addition, participants will 
  learn to perform a simple ABC inventory analysis.

Session 7-Inventory Management and Physical Distribution
  This session provides a discussion of inventory management and introduces
  physical distribution. Inventory management seeks to provide the required 
  level of customer service at minimum cost. Two basic questions of inventory
  management are explored: how much to order and when to order. The session 
  also provides participants with an understanding of some elements of a 
  physical distribution system. The order point concept, the economic order
  quantity, and service level are also discussed.

Session 8--Physical Distribution, Quality Management, and Purchasing
  This session continues the discussion of physical distribution. The next 
  topic, quality management, is a series of problem detection and problem 
  solving techniques that help employees and management address the problems 
  associated with producing a perfect product every time. The session teaches
  basic techniques for quality management, including Pareto analysis and 
  fishbone diagrams. The session concludes with a brief discussion of
  purchasing .

Session 9--Just-in-Time Manufacturing
  Just-in-Time is a philosophy that defines how a company organizes and oper-
  ates its business. This session shows how Just-in-Time manufacturing is an
  outcome of total quality management, basic industrial engineering practices,
  inventory management, process design, and product design.

Brief Bio of the instructor:

   Edward Kantor has over 30 years of experience in materials 
   management with various companies and has held positions in
   training, supplier partnership development, systems implementation,
   distribution, and materials management.

    

    
TITLE: Software-Oriented Memory-Management Design
Speaker:  Bruce Jacob, University of Michigan
Date: March 26th
Room: Mt. Washington Conf. Room, HLO2-1
Time: 10:00am - 12:00pm


ABSTRACT:

Software-Oriented Memory-Management Design
or
Virtual Memory in the Age of Cheap Memory

Bruce Jacob
Advanced Computer Architecture Lab
EECS Department, University of Michigan


This talk describes the memory-management design of the PUMA processor -- a
high clock-rate microprocessor in which a simple design is a prerequisite
for a fast clock and a short design cycle.  Software-managed address
translation* is a design option that eliminates hardware support for address
translation, such as the translation lookaside buffer (TLB) found in nearly
every modern microarchitecture, and hardware page-table-walking state
machines found in the x86 and PowerPC architectures.  Elimination of the
address translation hardware simplifies the chip design and removes a large,
fully-associative structure from the processor's critical path.  We show that
software-managed address translation is just as efficient as hardware-managed
address translation, and it is much more flexible.  Operating systems such as
OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI)
for address translation using dedicated memory-management hardware.
Software-managed translation requires 0.05 CPI.  Mechanisms to support
such features as shared memory, superpages, sub-page protection, and sparse
address spaces can be defined completely in software, allowing much more
flexibility than in hardware-defined mechanisms.

* see <http://www.eecs.umich.edu/~blj/papers/HPCA-3.ps> for details

BIO:

Mr. Jacob received the A.B. in Mathematics from Harvard College, Cambridge,
in 1988, and the M.S. in Computer Science and Engineering from the University
of Michigan, Ann Arbor, in 1995.  He is currently a doctoral candidate in
Computer Science and Engineering at the University of Michigan, where he is
conducting research in computer architecture and operating systems in the
Advanced Computer Architecture Lab.  He has worked as a distributed system
architect and software engineer for the telecommunications startups Priority
Call Management and Boston Technology.

    

 
 
 
--------------------------------------------------------------------------------
                  ETE Technical Seminar Series Description
________________________________________________________________________________
Title             Engineering Compilers                                       
Speaker           Thomas Gross                  
Date              02-APR-97 - 02-APR-97
Time              10:00 - 12:00
Location          Hall White Mist HLO2-2/J6     
Course Number     74TSS-01
Registration      Not required for most seminars.  If registration
                  is required please log into COURSES software on SHARE 
                   Username is COURSES and password is EDUCATION.

Description       Optimizing and parallelizing compilers
                  have the reputation to be big and complex; the
                  development of a competitive compiler system
                  represents a major effort.  The cmcc compiler
                  (Carnegie Mellon C Compiler) is an experiment
                  in compiler construction to challenge this view.
                  Through agressive code reuse- -- both internally
                  (reuse between different modules) and externally
                  (reuse between versions for different target
                  machines) -- a small team of graduate students
                  and faculty was able to build an optimizing
                  compiler. The key to reuse are the application
                  frameworks developed for global dataflow analysis,
                  code generation, register allocation, and
                  instruction scheduling.
                                                                                
                  This talk describes these frameworks and provides
                  some empirical evaluation might be extended to
                  cover difficult problems in the design of
                  parallelizing compilers.  Using the Fx compiler
                  (for a dialect of High Performance Fortran) as
                  an example, I discuss how we may extend such a
                  compiler to deal with  problems currently beyond
                  the scope of most parallelizing compilers,
                  e.g., programs  with irregular reference patterns
                  or programs with dynamic tasking.
 
--------------------------------------------------------------------------------
Engineering Training and Education
Supporting Digital Semiconductor

    

 
 
--------------------------------------------------------------------------------
                  ETE Technical Seminar Series Description
________________________________________________________________________________
Title             Global Register Allocation Based on Graph Fusion            
Speaker           Guei-Yuan (Ken) Lueh          
Date              08-APR-97 - 08-APR-97
Time              10:00 - 12:00
Location          Mt. Washington HLO2-1/M10     
Course Number     74TSS-02
Registration      Not required for most seminars.  If registration
                  is required please log into COURSES software on SHARE 
                   Username is COURSES and password is EDUCATION.
Cancellation      No Registration required                                    
                                                                              

Description       In the seminar, I present a novel register-
                  allocation that is fusion-based.  Fusion-style
                  register allocation starts off with constructing
                  regions and applies graph fusion along control-flow
                  edges to combine the interference graphs of regions
                  into the interference graph for the whole function.
                  Graphs fusion integrates spilling, splitting, and color
                  binding in a seamless fashion.  The delayed spilling
                  technique avoids making premature spilling decisions,
                  and maintaining the colorablity invariant splits live
                  ranges only when necessary.  No color binding decisions
                  are ever made during graph fusion.  More importantly,
                  fusion-style coloring is sensitive to the ordering of
                  control-flow edges that connect regions.  Splitting is
                  unlikely to happen at high priority edges (frequently
                  executed) and likely to happen at low priority edges
                  (infrequently executed).  As to fusion-style coloring,
                  the register-allocation problem becomes a problem of
                  determining the edge ordering and selecting regions.
                  Fusion-style coloring provides a nice framework for
                  register allocation which models various live-range
                  splitting approaches such allocation which models
                  various live-range splitting approaches such as the
                  Tera, SSA, PDG, and Multiflow approaches.
                                                                                
                  In my dissertation, I've shown that fusion-style
                  register allocation provides a framework that is
                  well-suited for region-based compilation and is
                  able to deal with the incurred register pressure
                  caused by scope expanding transformations such as
                  unrolling and inlining.  In other words, fusion-style
                  coloring provides a solution to region-based compilation
                  so that register allocation is no longer an obstacle
                  to region based compilation.
 
--------------------------------------------------------------------------------
Engineering Training and Education
Supporting Digital Semiconductor

    

    ---------------------------------------------------------------------------
                  EDE Technical Seminar Series Description
    ---------------------------------------------------------------------------
    
    
Title:      Technical Achievement at Digital Semiconductor
Speakers:   Maurice Marks, Don Scott, Christina Pomiansky
Date:       April 23rd, 1997
Time:       10:00am - 11:30
Location:   Cafe' Annex,  HLO2-2

Abstract:

     The objective of this presentation is to promote a better understanding
     of the Corporate and Digital Semiconductor procedures for recognizing
     innovation and technical achievement.  Specifically this presentation
     will discuss the mechanics of the Consulting Engineering Review Board,
     the procedures for Patents, Publications and Conferences as well as
     recognition awards such as the Chairman's Award for Technical Acheive-
     ment.

     Intended Audience:  Engineers in Digital Semiconductor who wish to
     have a better understanding of the mechanics of the Consulting Eng-
     ineer Review Board and it's components as well as Managers who are
     in a position to reward individuals for technical achievement.

     BRIEF OUTLINE:

                    Introduction  -  Christina Pomiansky
                    CERB - Maurice Marks
                    Patents/Publications  - Don Scott
                    Questions and Answers  - Christina, Maurice and Don

     

Employee Development and Education
Supporting Digital Semiconductor
    
    

Title: Path-based Compilation
Instructor: Cliff Young, Harvard University
Date:  April 7th
Time: 10:00am - 12:00pm
Room: Mt. Washington Conf. Room HLO2-1

Abstract:

Many compilers use _profiles_ of user program runs to direct the
focus and degree of performance optimizations.  Compilation systems
typically collect profiles by recording statistics at individual
points in the program text, e.g. branches, call sites, or memory
accesses.  But optimizations based on individual sample points in
the program miss the larger picture of program behavior: how pieces
of the program relate to each other dynamically.  By instrumenting
and collecting _path profiles_ of a program, we can perform more
sophisticated and accurate optimizations than classical point-wise
techniques have allowed.

In this talk, I discuss efficient path profiling techniques and
two applications of path profiles: static branch prediction and
global instruction scheduling.  Path profiles can be collected with
overheads comparable to those of traditional pointwise profiling
techniques.  Using path information, _static correlated branch
prediction_ exhibits better branch prediction accuracy and larger
performance improvements than previously thought possible for static
prediction techniques.  _Superblock_ global instruction scheduling
can benefit from the increased precision of path profiles: path
profiles simplify superblock selection and accounting.

Path-based techniques apply to both hardware- and software- oriented
optimizations.  Other fruitful areas for path-based methods include
instruction and data prefetching, predicated, and speculative
execution.

    

                                 
Title              Dataflow Microprocessors                                   
Speaker            Prof. Bradley Kuszmaul       
Date              10-APR-97 - 10-APR-97
Time              10:00 - 12:00
Location          Mt Washington HLO2-1/M10      
Course Number     74TSS-06
Registration      Not required                                            
Abstract:         My new research direction at Yale is to
                  explore the hypothesis that explicit-dataflow
                  instruction-set architectures provide significant
                  advantages for high-performance microprocessors.
                  This talk presents preliminary work comparing
                  serial instruction-set architectures (RISC or CISC)
                  vs. dataflow in achieving high parallelism on serial
                  programs.  I will describe several interesting dataflow
                  problems (and our progress at solving them), including
                  resource management, code-size blowup, and compiling
                  C programs for parallelism.
                                                                                
BIO:              Bradley C. Kuszmaul received his Ph.D. from MIT in 1994,
                  and worked as a postdoctoral fellow at MIT for a year.
                  At MIT he participated in the Cilk project and worked
                  on two massively parallel chess programs: StarTech and
                  *Socrates.  During his graduate student tenure he took
                  time off from MIT to serve as one of the principal
                  architects of the Connection Machine CM-5 at Thinking
                  Machines Corporation.  Bradley joined the Yale University
                  Department of Computer Science in 1995.
 
--------------------------------------------------------------------------------
Engineering Training and Education
Supporting Digital Semiconductor

    

                                               
--------------------------------------------------------------------------------
                  ETE Technical Seminar Series Description
________________________________________________________________________________
Title             Global Register Allocation Based on Graph Fusion            
Speaker           Guei-Yuan (Ken) Lueh          
Date              08-APR-97 - 08-APR-97
Time              1:00pm - 2:30pm
Location          Ad Hoc Conf. Room, HLO2-3/J03     
Course Number     74TSS-02
Registration      Not required for most seminars.  If registration
                  is required please log into COURSES software on SHARE 
                   Username is COURSES and password is EDUCATION.
Cancellation      No Registration required                                    
                                                                              

Description       In the seminar, I present a novel register-
                  allocation that is fusion-based.  Fusion-style
                  register allocation starts off with constructing
                  regions and applies graph fusion along control-flow
                  edges to combine the interference graphs of regions
                  into the interference graph for the whole function.
                  Graphs fusion integrates spilling, splitting, and color
                  binding in a seamless fashion.  The delayed spilling
                  technique avoids making premature spilling decisions,
                  and maintaining the colorablity invariant splits live
                  ranges only when necessary.  No color binding decisions
                  are ever made during graph fusion.  More importantly,
                  fusion-style coloring is sensitive to the ordering of
                  control-flow edges that connect regions.  Splitting is
                  unlikely to happen at high priority edges (frequently
                  executed) and likely to happen at low priority edges
                  (infrequently executed).  As to fusion-style coloring,
                  the register-allocation problem becomes a problem of
                  determining the edge ordering and selecting regions.
                  Fusion-style coloring provides a nice framework for
                  register allocation which models various live-range
                  splitting approaches such allocation which models
                  various live-range splitting approaches such as the
                  Tera, SSA, PDG, and Multiflow approaches.
                                                                                
                  In my dissertation, I've shown that fusion-style
                  register allocation provides a framework that is
                  well-suited for region-based compilation and is
                  able to deal with the incurred register pressure
                  caused by scope expanding transformations such as
                  unrolling and inlining.  In other words, fusion-style
                  coloring provides a solution to region-based compilation
                  so that register allocation is no longer an obstacle
                  to region based compilation.
 
--------------------------------------------------------------------------------
Engineering Training and Education
Supporting Digital Semiconductor

    
    

    
       Please note that the seminar on Dataflow Microprocessors (Note
    160.155)  by Dr. Kuszmaul has been cancelled.
    
       We are currently checking alternative dates and hope to reschedule
    shortly.
    
    /pjs

TITLE:   Branch Classification
Speaker:  Po-Yung Chang
Date: April 28th
Location:  Mt. Washington, HLO2-1
Time: 11:00am - 12:30pm

Abstract:

As the issue rate and pipeline depth increase for high performance
superscalar processors, the amount of speculative work issued for such
processors also increases.  Because speculative work must be thrown
away in the event of a branch misprediction, wide-issue, deeply
pipelined processors must use extremely accurate branch predictors to
effectively exploit their performance potential.

Several mechanisms exist to address the problems posed by 
branches; each of these mechanisms has its own sphere of relevance.
Our work in branch classification looks to identify a set of
mechanisms that will cover the needs of all branches and
to identify the appropriate mechanism to use for each branch.

This talk will present our work in branch classification.
It will describe various branch mechanisms, e.g. 2-level 
branch predictors and loop predictors.  It will also
describe various branch classification schemes, e.g. 2 bit counter
schemes and a branch filtering mechanism, to show how
branch classification can be used to improve branch prediction 
accuracy.
                                   

    

                                 
Title              Dataflow Microprocessors                                   
Speaker            Prof. Bradley Kuszmaul       
Date              May 13th
Time              10:00 - 12:00
Location          Mt Washington HLO2-1/M10      
Course Number     74TSS-06
Registration      Not required                                            
Abstract:         My new research direction at Yale is to
                  explore the hypothesis that explicit-dataflow
                  instruction-set architectures provide significant
                  advantages for high-performance microprocessors.
                  This talk presents preliminary work comparing
                  serial instruction-set architectures (RISC or CISC)
                  vs. dataflow in achieving high parallelism on serial
                  programs.  I will describe several interesting dataflow
                  problems (and our progress at solving them), including
                  resource management, code-size blowup, and compiling
                  C programs for parallelism.
                                                                                
BIO:              Bradley C. Kuszmaul received his Ph.D. from MIT in 1994,
                  and worked as a postdoctoral fellow at MIT for a year.
                  At MIT he participated in the Cilk project and worked
                  on two massively parallel chess programs: StarTech and
                  *Socrates.  During his graduate student tenure he took
                  time off from MIT to serve as one of the principal
                  architects of the Connection Machine CM-5 at Thinking
                  Machines Corporation.  Bradley joined the Yale University
                  Department of Computer Science in 1995.
 
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Engineering Training and Education
Supporting Digital Semiconductor

    
    

 
 
   ETE - Engineering Training and Education
 
 
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                  ETE Technical Seminar Series Description
________________________________________________________________________________
Title             RELIABILITY AND STRENGTH  OF  METALLIZATIONS                
Speaker           G.L. Povirk, Yale University  
Date              27-MAY-97 - 27-MAY-97
Time              10:00 - 12:00
Location          Mt. Washtington HLO2-1/J10    
Course Number     74TSS-09
Registration      Not required for most seminars.  If registration
                  is required please log into COURSES software on SHARE 
                   Username is COURSES and password is EDUCATION.

Abstract:         Two distinct aspects of metallization
                  reliability in microelectronic circuits will
                  be discussed.  The first part of the presentation
                  will focus on finite element simulations of
                  electromigration and stress-driven diffusion
                  in metal interconnects.  The numerical formulation
                  accounts for diffusion both along grain boundaries
                  and through the bulk.  A polycrystaline line is
                  considered and the effects of diffusion along
                  individual grain boundaries and through the bulk
                  are each added seperately to the analysis.
                                                                                
                  The ultimate strength of the films was up to
                  three times that of bulk gold, with the thinnest
                  films exhibiting the greatest strength. In contrast,
                  the measured elastic modulus for the thin film
                  specimens was approximately the same as that
                  documented for bulk gold.  The presentation
                  will conclude with plans for future work.
 
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Engineering Training and Education
Supporting Digital Semiconductor

    

 
 
   ETE - Engineering Training and Education
 
 
--------------------------------------------------------------------------------
                  ETE Technical Seminar Series Description
________________________________________________________________________________
Title             The Improvement Paradox:Designing Sustainable Quality Progra
Speaker           John D. Sterman, MIT          
Date              02-JUN-97 - 02-JUN-97
Time              1:00 -  4:00
Location          Mt. Washington Conf.HLO2-1/M10
Course Number     74TSS-11
Registration      REGISTRATION IS REQUIRED

Abstract                                                                        
                  Organizations today must constantly improve
                  their business processes in all functions and product
                  lines.  To stimulate change and boost competitiveness,
                  companies have adopted a wide range of process
                  improvement methods including TQM, CQI, BPR, and so on.
                  Despite notable successes, there have been even more
                  failures.  Even initially successful programs often
                  fail later.  Management constantly searches for the
                  next magic bullet as program after program fails to
                  live up to expectations.  For example, interest in
                  the Malcolm Baldrige National Quality Award is falling,
                  and press reports skeptical of TQM and reengineering
                  are common, despite the obvious successes of some
                  companies.  Worse, many successful programs fail to
                  generate financial results or prevent significant
                  downsizing, leading to their abandonment:
                  the improvement paradox.
                                                                                
                  Why is it so difficult to design sustainable process
                  improvement programs?  This presentation will describe
                  ongoing research at the MIT System Dynamics Group into
                  the causes of the improvement paradox in partnership
                  with leading firms in the electronics and automotive
                  industries.  The focus is helping managers avoid
                  unanticipated consequences of improvement programs
                  arising from feedbacks between improvement efforts
                  and other stakeholders and organizations in the
                  firm, including feedbacks among quality programs,
                  manufacturing, product development, accounting
                  systems and performance metrics, customers,
                  competitor reactions, and the stock market.
                                                                                
                  To explore these dynamics we have developed system
                  dynamics simulation models, grounded in extensive
                  field study with several partner organizations.
                  I will present several case studies to illustrate
                  the issues.  For example, one leading semiconductor
                  manufacturer pursued an aggressive process improvement
                  program to boost productivity and competitiveness.
                  The program was a dramatic success.  Yield doubled,
                  cycle time was cut in half, and product defects fell
                  by a factor of ten. However, financial performance
                  worsened and the firm was forced into layoffs,
                  destroying morale and commitment to the improvement
                  program.
                  Improvement programs can present firms with a tradeoff
                  between short and long run effects.  In the long run
                  they can increase productiv-ity, raise quality, and
                  lower costs.  In the short run, these improvements
                  can create excess capacity, financial stress, and
                  pressures for layoffs that undercut commitment to
                  continuous improvement.  I discuss policies
                  to deal with these side effects and effective

                  learning strategies for firms seeking to overcome
                  the improvement paradox.
                                                                                
                  John Sterman is the Standish Professor of Management
                  and the Director of the System Dynamics Group at MIT's
                  Sloan School of Management
 
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Engineering Training and Education
Supporting Digital Semiconductor