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STRATUS ATM ADAPTER ENGINEERING REQUIREMENTS
1.0 Hardware/Firmware Requirements
1.1 Bus
1.1.1 PCI Support
The bus architecture for the adapter must be PCI.
1.1.1.1 PCI 2.1 Revision Compliance
The PCI bus must be compliant to the following specifications:
a) PCI Local Bus Specification Revision 2.1. June 1. 1995.
b) PCI Compliance Checklist Rev 2.1b.
1.1.1.2 Miscellaneous/Informational
Specify the following for the adapter:
1. Bus data transfer bandwidth (MB/sec)
2. Bus clock rate
3. Bus data path width (n-bit)
4. Bus operating voltage and watt requirements
5. Adapter operating mode (bus master, slave, or both)
6. Does the adapter support special cycles?
7. Does the adapter support fast back-to-back cycles?
8. What is the DEVSEL time? Slow, Medium or Fast?
9. How is the PCI LOCK# signal used? only as an input?
10. How is the SERR# signal used?
-> Only as an output?
-> Does it affect master/slave state machines directly?
11. Does your adapter conform to the following statement if it
is 2.1 compliant?
Repeat Request Terminated With Retry' - "A master which is target terminated
with Retry MUST UNCONDITIONALLY REPEAT THE SAME REQUEST UNTIL IT COMPLETES"
(my emphasis). Other requests may interleave with the retry of the original
request as long as the original request is guaranteed to be retried until it
is completed, regardless of the termination type of any interleaved
transactions.
1.1.2 PMC Form Factor Support
The support of PMC form factor is desired.
Draft Standard Physical and Environmental Layers for PCI Mezzanine cards:PMC
P1386.1/Draft 2.0,04-April-1995.
Draft Standard for a Common Mezzanine Card Family:CMC. P1386/Draft 2.0,
04-April-1995.
1.2 Adapter Design
1. Specify if the adapter is an intelligent adapter with on
board CPU. (microprocessor)
2. Specify what interface is used for the PCI bus?
Proprietary ASIC or off the shelf.
3. Specify the size of on-board RAM and the use of it.
1.3 Adapter Physical
1.3.1 LED Indicators
The adapter must contain at least one (1) link status LED that is easily
visible.
1.3.2 Jumpers
No user-settable jumper or switch is allowed on the adapter.
1.3.3 Operating Environment
The adapter must conform to the following specifications:
1. Operating Temperature 0 to 40 degrees C.
2. NonOperating Temperature -40 to 70 degrees C.
3. Operating Humidity 15% to 80% Relative Humidity, non-condensing.
4. Operating Altitude 0 to 15,000 ft.
5. NonOperating Altitude 0 to 50,000 ft.
1.3.4 Operating Frequency
1.3.4.1 PCI Frequency
Can you run from 0 to 33MHZ? Can you run spcifically at 24 MHZ? This
is an absolute requirements fro our system.
1.3.4.2 Board Frequency
What is the frequency of the on board oscillator?
1.3.5 MTBF
What is your MTBF? Calculated? Measured?
1.4 Agency Compliance Requirements
1.4.1 Emissions
FCC Part 15, Subpart J, Class B
CSA C108.8-M83, Class B
CISPR 22, Class B
1.4.2 Safety
UL recognized. UL 1950
CSA certified, CSA C22.2 No.220
IEC 380/950 Safety(TUV)
1.4.3 Immunity
EN 50082(IEC 801)
1.5 Cabling and Connector
1. Support for 155 Mbps OC-3c multimode-fiber with SC and ST
connector is required.
2. Support for 155 Mbps OC-3c Category 5 copper with UTP RJ45
connector is desired.
3. Support for 155 Mbps OC-3c singlemode-fiber with SC and ST
connector is desired.
2.0 ATM Functionality Support
2.1 Physical Layer
SONET STS-3c and SDH-3 must be supported.
2.2 ATM Layer
Specify UNI 3.1 ATM layer functions that are not supported.
2.3 AAL Layer
1. Specify UNI 3.1 AAL layer functions that are not supported.
2. Specify the number of VCC that is supported.
2.4 Management
Specify UNI 3.1 layer management functions that are not supported in
physical, ATM, and AAL layers.
2.5 Signalling
1. Both UNI 3.0 and 3.1 Signalling must be supported. The selection
of UNI 3.0 or 3.1 must be a run-time option.
2. Specify UNI 3.0/3.1 Signalling functions that are not supported.
2.6 RFC 1577
1. RFC 1577 over both PVC and SVC must supported.
2. Specify RFC 1577 functions that are not supported.
2.7 LAN Emulation
1. LANE 1.0 must be supported.
2. Specify LANE 1.0 functions that are not supported.
3.0 ATM Standard Compliance
All ATM functions that are supported must be compliant to protocol standards
as defined by ATM Forum.
4.0 Host Adapter Interface
4.1 Configuration/Initialization
4.1.1 SONET/SDH
Host must be able to set the adapter to operate in either SONET or SDH mode.
4.1.2 ATM Adapter MAC Address
Host must be able to read and modify the adapter MAC address.
4.1.3 Adapter Reset
Host must be able to reset the adapter. The reset must cause all on-board
registers settings to default values.
4.2 Transmitting Packet
4.2.1 Simultaneous Packet Segmentation
1. Host must be able to set up the adapter for simultaneous packet
segmentation of multiple packets.
2. Specify the maximum number of packets that the adapter allows
for simultaneous packet segmentation.
4.2.2 Scatter-gathered DMA
Host must be able to transmit a packet consisting of multiple, non-contiguous
memory segments.
4.2.3 Host-initiated PCI Transactions
The number of PCI transactions that host has to perform to transmit a packet
must not exceed one (1) PCI read (from adapter to host) and two (2) PCI
writes (from host to adapter).
4.3 Receiving Packet
4.3.1 On-board/Host Packet Reassembly
Specify if the adapter supports on-board packet reassembly, or host
reassembly, or both.
4.3.2 Receive Buffer Size
Host must be able to set up the buffer pools of different buffer sizes for
packet reassembly, either on-board or host reassembly, in a way that small
packets only use small-size buffers.
4.3.3 DMA Burst Size
The burst size for DMA transfer of packet from the adapter to host must be
able to be set at 32-byte. This is due to the limitation of PCI bridge.
Burst size of more than 32-byte will cause serious performance problem.
4.3.4 Host-initiated PCI Transactions
The number of PCI transactions that host has to perform to receive a packet
must not exceed one (1) PCI read (from adapter to host) and two (2) PCI
writes (from host to adapter).
5.0 Software Requirement
5.1 Components
The following software components are required:
1. Host interface driver to the adapter
2. Signalling
3. RFC 1577
4. LANE Client (LEC)
5. ATM API
5.2 Operating System Support
It is desirable that the adapter and the required software are supported in
UNIX SVR4 environment, which implies for device driver, it is:
1. DDI/DKI compliance
2. DLPI compliance
3. Support streams
4. Support multi-processor environment
5.3 Software Portation
The adapter associated software is to be ported to Stratus system. Vendor is
to deliver to Stratus all source code and technical manuals/specifications.
Stratus ATM Adapter Engineering Requirements
5.3 Diagnostics
1. Do you provide diagnostics with the adapter?
2. What native environment can they be run in?
3. Are they located in on board PROM?
4. Are they loaded via a floppy?
6.0 Business requirements
6.1 Warranty
Specify your warranty period and coverage.
6.2 Software or Hardware changes
Do you have a system for notifying your customers of Software or Hardware
changes? (ECO's, etc.)
6.3 Manufacturing
Does your manufacturing processes conform to the following workmanship
standard?
ANSI/IPC-A-610 Class 2, current revision.
6.4 Support
1. Do you have a support hot line?
2. What level of coverage is provided?
(24 hour, 7 day a week or normal business hours?)
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| Ranjeet Sudan is the product manager ([email protected]). He owns
all ATM adapters.
Offhand, I have a few comments:
1. the 350 is going end-of-life. the 351 is the replacement.
2. the 32 byte maximum DMA size requirement will greatly hurt PCI
performance. the 350 does 256 byte DMA reads. the 351 does 48 byte
DMA reads. the 351 can be told which PCI read command to use (Read,
Read Line or Read Multiple). Beyond that, it always tries to get 48
bytes and will only stop in the middle if the host stops (in which case
it will ask again for the remainder). writes are not as big a
performance problem (since the PCI bus is not stalled waiting for read
data). The 351 does 48 byte DMA writes (again unless the host stops
it).
3. There is talk of doing a PMC formfactor version of the 351. Ranjeet
is making the business case. It might be a CSS product.
Other stuff... (answers are for the 351).
1.1.1.2 Miscellaneous/Informational
Specify the following for the adapter:
1. Bus data transfer bandwidth (MB/sec)
PCI will do 132 Mbytes/sec theoretical (if every cycle is a data
cycle -- not realizable in real systems). 100 Mbytes/sec is more
reasonable.
2. Bus clock rate
up to 33 Mhz
3. Bus data path width (n-bit)
32 Bit PCI
4. Bus operating voltage and watt requirements
We've tested it on 5Volt PCI. Wattage depends on RAM sizes and
physical layer (MMF, SMF, UTP). I'm not sure of the numbers.
5. Adapter operating mode (bus master, slave, or both)
Both
6. Does the adapter support special cycles?
No
7. Does the adapter support fast back-to-back cycles?
I forget -- I'll look it up (I'm at home right now).
8. What is the DEVSEL time? Slow, Medium or Fast?
Medium
9. How is the PCI LOCK# signal used? only as an input?
No
10. How is the SERR# signal used?
-> Only as an output?
Yes
-> Does it affect master/slave state machines directly?
Not sure about what they want here
11. Does your adapter conform to the following statement if it
is 2.1 compliant?
Yes
1.2 Adapter Design
1. Specify if the adapter is an intelligent adapter with on
board CPU. (microprocessor)
No processor, 1 chip adapter (plus RAM and SUNI and Etherenet address
ROM)
2. Specify what interface is used for the PCI bus?
Proprietary ASIC or off the shelf.
The Meteor ASIC will be available from Toshiba.
3. Specify the size of on-board RAM and the use of it.
The ON-board RAM is used for schedule table storage, command queue
storage and virtual curcuit state. I forget the RAM size (I'm at home
right now).
1.3.4.1 PCI Frequency
Can you run from 0 to 33MHZ? Can you run spcifically at 24 MHZ? This is
an absolute requirements fro our system.
We've only tested it at clock rates near 33Mhz. I think we've put in a
30Mhz system, but not much slower than that.
Steveg
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